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Table of Contents


The Trenz Electronic TE0807 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, up to 8 GBytes of DDR4 SDRAM via 64bit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the competitive price.

Use short link the Wiki Ressource page: for example:
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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3. A PNG Export of the diagram has to be inserted in the "Scroll Only" macro 

The workaround with the additional PNG of the diagram is necessary until the bug of the Scroll PDF Exporter, which cuts diagram to two pages, is fixed.

IMPORTANT NOTE: In case of copy and paste the TRM skeleton to a new Wiki page, delete the Draw.IO diagrams and the PNGs, otherwise due to the linkage of the copied diagrams every change in the TRM Skeleton will effect also in the created TRM and vice versa!

See page "Diagram Drawing Guidelines" how to clone an existing diagram as suitable template for the new diagram! 


Main Components

  1. Xilinx ZYNQ UltraScale+ ZU7EV-1FBVB900 MPSoC, U1
  2. EN63A0QI 12A PowerSoC DC-DC converter, U4
  3. TI TPS72018 LDO @1.8V, U6
  4. TI TPS74401 LDO @0.9V, U14
  5. TI TPS74401 LDO @1.2V, U28
  6. TI TPS72018 LDO @1.8V, U6
  7. Quarz Crystal @50.000MHz, Y1
  8. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
  9. TI TPS74801 LDO @1.8V, U10
  10. TI TPS74801 LDO @0.9V, U8
  11. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U12
  12. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
  13. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
  14. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  18. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  19. 1.8V, 512 Mbit QSPI flash memory ,U17
  20. 1.8V, 512 Mbit QSPI flash memory, U7
  21. TI TPS72018 LDO @1.8V, U27

Initial Delivery State

 Storage Device Name



SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit



SPI Flash main array

Not programmed



Not programmed


eFUSE Security

Not programmed

Si5345A OTP NVMNot programmed-

Table 1: Initial delivery state of programmable devices on the module

Boot Process

The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:

Boot Mode PinB2B Pin

Table 2: Boot mode pins on B2B connector J2.

Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):

Boot ModeMode Pins [3:0]MIO LocationDescription
JTAG0x0JTAGDedicated PS interface.

Configured on module with dual QSPI Flash Memory.

32-bit addressing.
Supports single and dual parallel
Stack and dual stack is not

SD00x3MIO[25:13]Supports SD 2.0.
SD10x5MIO[51:38]Supports SD 2.0.
eMMC_180x6MIO[22:13]Supports eMMC 4.5 at 1.8V.
USB 00x7MIO[52:63]Supports USB 2.0 and USB 3.0.
PJTAG_00x8MIO[29:26]PS JTAG connection 0 option.

Supports SD 3.0 with a required SD 3.0 compliant level shifter.

Table 3: Selectable boot modes by dedicated boot mode pins

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0807 MPSoC SoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltraScale+ MPSoC like I/O banks, interfaces and Gigabit transceivers
or to the on-board peripherals.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

BankTypeB2B ConnectorI/O Signal CountBank VoltageNotes
47HDJ324 single-ended I/Os or 12 LVDS pairs


VCCO max. 3.3V

48HDJ324 single-ended I/Os or 12 LVDS pairs


VCCO max. 3.3V

64HPJ452 single-ended I/O's or 24 LVDS pairs


VCCO max. 1.8V

65HPJ452 single-ended I/Os or 24 LVDS pairs


VCCO max. 1.8V

66HPJ152 single-ended I/Os or 24 LVDS pairs


VCCO max. 1.8V

500MIOJ313 I/OsPS_1V8User configurable I/Os on B2B
501MIOJ326 I/OsPS_1V8User configurable I/Os on B2B
502MIOJ326 I/OsPS_1V8User configurable I/Os on B2B

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the B2B pin-out, please refer to the Pin-out table. 

The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The Xilinx Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

BankTypeLaneSignal NameB2B PinFPGA Pin
  • B224_RX0_P
  • B224_RX0_N
  • B224_TX0_P
  • B224_TX0_N
  • J1-69
  • J1-71
  • J1-68
  • J1-70
  • MGTHRXP0_224, V2
  • MGTHRXN0_224, V1
  • MGTHTXP0_224, W4
  • MGTHTXN0_224, W3
  • B224_RX1_P
  • B224_RX1_N
  • B224_TX1_P
  • B224_TX1_N
  • J1-63
  • J1-65
  • J1-62
  • J1-64
  • MGTHRXP1_224, U4
  • MGTHRXN1_224, U3
  • MGTHTXP1_224, V6
  • MGTHTXN1_224, V5
  • B224_RX2_P
  • B224_RX2_N
  • B224_TX2_P
  • B224_TX2_N
  • J1-57
  • J1-59
  • J1-56
  • J1-58
  • MGTHRXP2_224, T2
  • MGTHRXN2_224, T1
  • MGTHTXP2_224, T6
  • MGTHTXN2_224, T5
  • B224_RX3_P
  • B224_RX3_N
  • B224_TX3_P
  • B224_TX3_N
  • J1-51
  • J1-53
  • J1-50
  • J1-52
  • MGTHRXP3_224, P2
  • MGTHRXN3_224, P1
  • MGTHTXP3_224, R4
  • MGTHTXN3_224, R3
  • B225_RX0_P
  • B225_RX0_N
  • B225_TX0_P
  • B225_TX0_N
  • J1-45
  • J1-47
  • J1-44
  • J1-46
  • MGTHRXP0_225, N4
  • MGTHRXN0_225, N3
  • MGTHTXP0_225, P6
  • MGTHTXN0_225, P5
  • B225_RX1_P
  • B225_RX1_N
  • B225_TX1_P
  • B225_TX1_N
  • J1-39
  • J1-41
  • J1-38
  • J1-40
  • MGTHRXP1_225, M2
  • MGTHRXN1_225, M1
  • MGTHTXP1_225, M6
  • MGTHTXN1_225, M5
  • B225_RX2_P
  • B225_RX2_N
  • B225_TX2_P
  • B225_TX2_N
  • J1-33
  • J1-35
  • J1-32
  • J1-34
  • MGTHRXP2_225, K2
  • MGTHRXN2_225, K1
  • MGTHTXP2_225, L4
  • MGTHTXN2_225, L3
  • B225_RX3_P
  • B225_RX3_N
  • B225_TX3_P
  • B225_TX3_N
  • J1-27
  • J1-29
  • J1-26
  • J1-28
  • MGTHRXP3_225, J4
  • MGTHRXN3_225, J3
  • MGTHTXP3_225, K6
  • MGTHTXN3_225, K5
  • B226_RX0_P
  • B226_RX0_N
  • B226_TX0_P
  • B226_TX0_N
  • J1-21
  • J1-23
  • J1-20
  • J1-22
  • MGTHRXP0_226, H2
  • MGTHRXN0_226, H1
  • MGTHTXP0_226, H6
  • MGTHTXN0_226, H5
  • B226_RX1_P
  • B226_RX1_N
  • B226_TX1_P
  • B226_TX1_N
  • J1-15
  • J1-17
  • J1-14
  • J1-16
  • MGTHRXP1_226, G4
  • MGTHRXN1_226, G3
  • MGTHTXP1_226 G8
  • MGTHTXN1_226, G7
  • B226_RX2_P
  • B226_RX2_N
  • B226_TX2_P
  • B226_TX2_N
  • J1-9
  • J1-11
  • J1-8
  • J1-10
  • MGTHRXP2_226, F2
  • MGTHRXN2_226, F1
  • MGTHTXP2_226, F6
  • MGTHTXN2_226, F5
  • B226_RX3_P
  • B226_RX3_N
  • B226_TX3_P
  • B226_TX3_N
  • J1-3
  • J1-5
  • J1-2
  • J1-4
  • MGTHRXP3_226, E4
  • MGTHRXN3_226, E3
  • MGTHTXP3_226, E8
  • MGTHTXN3_226, E7
  • B227_TX0_P
  • B227_TX0_N
  • B227_RX0_P
  • B227_RX0_N
  • J2-45
  • J2-43
  • J2-48
  • J2-46
  • MGTHRXP0_227, D1
  • MGTHRXN0_227, D2
  • MGTHTXP0_227, D5
  • MGTHTXN0_227, D6
  • B227_TX1_P
  • B227_TX1_N
  • B227_RX1_P
  • B227_RX1_N
  • J2-39
  • J2-37
  • J2-42
  • J2-40
  • MGTHRXP1_227, C3
  • MGTHRXN1_227, C4
  • MGTHTXP1_227, C7
  • MGTHTXN1_227, C8
  • B227_TX2_P
  • B227_TX2_N
  • B227_RX2_P
  • B227_RX2_N
  • J2-33
  • J2-31
  • J2-36
  • J2-34
  • MGTHRXP2_227, B1
  • MGTHRXN2_227, B2
  • MGTHTXP2_227, B5
  • MGTHTXN2_227, B6
  • B227_TX3_P
  • B227_TX3_N
  • B227_RX3_P
  • B227_RX3_N
  • J2-27
  • J2-25
  • J2-30
  • J2-28
  • MGTHRXP3_227, A3
  • MGTHRXN3_227, A4
  • MGTHTXP3_227, A7
  • MGTHTXN3_227, A8
  • B505_TX0_P
  • B505_TX0_N
  • B505_RX0_P
  • B505_RX0_N
  • J2-69
  • J2-67
  • J2-72
  • J2-70
  • PS_MGTRRXP0_505, M27
  • PS_MGTRRXN0_505, M28
  • PS_MGTRTXP0_505, L29
  • PS_MGTRTXN0_505, L30
  • B505_TX1_P
  • B505_TX1_N
  • B505_RX1_P
  • B505_RX1_N
  • J2-63
  • J2-61
  • J2-66
  • J2-64
  • PS_MGTRRXP1_505, K27
  • PS_MGTRRXN1_505, K28
  • PS_MGTRTXP1_505, J29
  • PS_MGTRTXN1_505, J30
  • B505_TX2_P
  • B505_TX2_N
  • B505_RX2_P
  • B505_RX2_N
  • J2-57
  • J2-55
  • J2-60
  • J2-58
  • PS_MGTRRXP2_505, J25
  • PS_MGTRRXN2_505, J26
  • PS_MGTRTXP2_505, H27
  • PS_MGTRTXN2_505, H28
  • B505_TX3_P
  • B505_TX3_N
  • B505_RX3_P
  • B505_RX3_N
  • J2-51
  • J2-49
  • J2-54
  • J2-52
  • PS_MGTRRXP3_505, G25
  • PS_MGTRRXN3_505, G26
  • PS_MGTRTXP3_505, G29
  • PS_MGTRTXN3_505, G30

Table 5: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board. The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Clock signalBankSourceFPGA PinNotes
B224_CLK0_P224B2B, J3-62MGTREFCLK0P_224, R8Supplied by the carrier board
B224_CLK0_N224B2B, J3-60MGTREFCLK0N_224, R7Supplied by the carrier board
B224_CLK1_P224U5, CLK4_PMGTREFCLK1P_224, N8On-board Si5345A
B224_CLK1_N224U5, CLK4_NMGTREFCLK1N_224, N7On-board Si5345A
B225_CLK0_P225B2B, J3-67MGTREFCLK0P_225, L8Supplied by the carrier board
B225_CLK0_N225B2B, J3-65MGTREFCLK0N_225, L7Supplied by the carrier board
B225_CLK1_P225U5, CLK3_PMGTREFCLK1P_225, J8On-board Si5345A
B225_CLK1_N225U5, CLK3_NMGTREFCLK1N_225, J7On-board Si5345A
B226_CLK0_P226U5, CLK2_PMGTREFCLK0P_226, H10On-board Si5345A
B226_CLK0_N226U5, CLK2_NMGTREFCLK0N_226, H9On-board Si5345A
B226_CLK1_P226B2B, J3-61MGTREFCLK1P_226, F10Supplied by the carrier board
B226_CLK1_N226B2B, J3-59MGTREFCLK1N_226, F9Supplied by the carrier board
B227_CLK0_P227U5, CLK1_PMGTREFCLK0P_227, D10On-board Si5345A
B227_CLK0_N227U5, CLK1_NMGTREFCLK0N_227, D9On-board Si5345A
B227_CLK1_P227B2B, J2-22MGTREFCLK1P_227, B10Supplied by the carrier board
B227_CLK1_N227B2B, J2-24MGTREFCLK1N_227, B9Supplied by the carrier board
B505_CLK0_P505B2B, J2-10PS_MGTREFCLK0P_505, M23Supplied by the carrier board
B505_CLK0_N505B2B, J2-12PS_MGTREFCLK0N_505, M24Supplied by the carrier board
B505_CLK1_P505B2B, J2-16PS_MGTREFCLK1P_505, L25Supplied by the carrier board
B505_CLK1_N505B2B, J2-18PS_MGTREFCLK1N_505, L26Supplied by the carrier board
B505_CLK2_P505U5, CLK5_PPS_MGTREFCLK2P_505, K23On-board Si5345A
B505_CLK2_N505U5, CLK5_NPS_MGTREFCLK2N_505, K24On-board Si5345A
B505_CLK3_P505U5, CLK6_PPS_MGTREFCLK3P_505, H23On-board Si5345A
B505_CLK3_N505U5, CLK6_NPS_MGTREFCLK3N_505, H24On-board Si5345A

Table 6: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

JTAG SignalB2B Connector Pin

Table 7: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed.
PROG_BJ2-100PL configuration reset signal.
INIT_BJ2-98PS is initialized after a power-on reset.
SRST_BJ2-96System reset.
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103

4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.


ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

PUDC_BJ2-127Pull-up during configuration (pulled-up to PL_1V8).

Table 8: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

SignalB2B Connector PinFunction
V_P, V_NJ2-113, J2-115System Monitor
DX_P, DX_NJ2-119, J2-121Temperature-sensing diode pins

Table 9: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

MIOSignal NameU7 Pin
MIOSignal NameU17 Pin
0SPI Flash CLKB2
7SPI Flash CS
1SPI Flash IO1
8SPI Flash IO0
2SPI Flash IO2
9SPI Flash IO1
3SPI Flash IO3D4
10SPI Flash IO2
4SPI Flash IO0
11SPI Flash IO3D4
5SPI Flash CS
12SPI Flash CLK

Table 10: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

PS MIOFunctionConnected to
1SPI0U7-D2, DO/IO1
2SPI0U7-C4, WP/IO2
4SPI0U7-D3, DI/IO0 
5SPI0 U7-C2, CS
6N/ANot connected
7SPI1U17-C2, CS
8SPI1U17-D3, DI/IO0
9SPI1U17-D2, DO/IO1
10SPI1U17-C4, WP/IO2
11SPI1U17-D4, HOLD/IO3
12SPI1U17-B2, CLK
13 ... 77user dependentB2B connector J2

Table 11: TE0807-03 PS MIO mapping

On-board Peripherals


The TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

SPI FlashN25Q512A11G1240EU7QSPI0MIO0 ... MIO5dual parallel booting possible, 64 MByte memory per Flash IC at standard configuration
SPI FlashN25Q512A11G1240EU17QSPI0MIO7 ... MIO12

Table 12: Peripherals connected to the PS MIO pins.


The TE0807-03 SoM is equipped with four DDR4 SDRAM chips with a total of up to 8 GByte memory. The SDRAM chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

InputConnected toFrequencyNotes
IN0On-board Oscillator (U25)25.000000 MHz-
IN1B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
XA/XBQuartz (Y1)50.000 MHz-
OutputConnected toFrequencyNotes
OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault off
OUT1B227 CLK0UserDefault off
OUT2B226 CLK0UserDefault off
OUT3B225 CLK1UserDefault off
OUT4B224 CLK1UserDefault off
OUT5B505 CLK2UserDefault off
OUT6B505 CLK3UserDefault off
OUT7B2B Connector pins J2-7, J2-9 (differential pair)UserDefault off
OUT8B2B Connector pins J2-13, J2-15 (differential pair)UserDefault off
OUT9IN3 (Loop-back)UserDefault off

Table 13: Programmable PLL clock generator input/output.

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency increment
PLL_LOLNJ2-85Loss of lock (active-low)
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual input switching
PLL_FDECJ2-94Frequency decrement

Device reset (active-low)

PLL_SCL / PLL_SDAJ2-90 / J2-92

I2C interface, external pull-ups needed for SCL / SDA lines

I2C address in current configuration: 1101001b.

Table 14: B2B connector pin-out of Si5345A programmable clock generator.

Si5345 OTP ROM is not programmed by default at delivery, so it is customers responsibility to either configure Si5345 during FSBL or then use SiLabs programmer and program the OTP ROM with customer fixed clock setup.

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.


The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

ClockSignal Schematic NameFrequencyConnected to Bank 503 Pin
MEMS Oscillator, U32PS_CLK33.333333 MHzBank 503 Pin P20
Quartz crystal, Y2XTALI / XTALO32.768 kHzBank 503 Pin R22/R23
Quartz crystal, Y1XAXB_P / XAXB_N50.000 MHzPLL U5, Pin XA/XB

Table 15: On-board osciallators


There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I2C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL).

On-board LEDs


ColorConnected toDescription and Notes
D1RedDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

Table 16: LED's description.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current

Table 17: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular external DC-DC converters.

The Processing System contains three Power Domains:

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

Each power domain has its own enable and power good signals. The power rail GT_DCDC is needed to generate the voltages for the Multi Gigabit Transceiver units of the Zynq UltraScale+ MPSoC.

Power Distribution Dependencies

The power rails DCDCIN, LP_DCDC, PL_DCIN, PS_BATT have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered from 3.3V power sources (also share the same source, if power domain control is not required).

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

Power-On Sequence

The TE0807 SoM meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0807 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

  1. Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
  2. Programmable Logic (PL) and Full-Power Domain (FPD)
  3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)

PG_PLJ2-1044K7, pulled up to PL_DCIN


EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74401 data sheet
EN_PLL_PWRJ2-776VTPS82085SIL data sheet
PG_PLL_1V8J2-80External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS82085SIL data sheet

Table 18: Recommended operation conditions of DC-DC converter control signals.

To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during power-on sequence.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.

Voltage Monitor Circuit

The voltages LP_DCDC and LP_0V85 are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

Power Rails

Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins


PL_DCIN151, 153, 155, 157, 159---Input-


154, 156, 158, 160,
153, 155, 157, 159

LP_DCDC-138, 140, 142, 144--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V nominal output


Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-

Table 19: TE0807-03 power rails

Bank Voltages

BankTypeSchematic NameVoltageReference Input VoltageVoltage Range
47HDVCCO47user-1.2V to 3.3V
48HDVCCO48user-1.2V to 3.3V
64HPVCCO64userVREF_64, pin J4-881.2V to 1.8V
65HPVCCO65userVREF_65, pin J4-151.2V to 1.8V
66HPVCCO66userVREF_66, pin J1-1081.2V to 1.8V

Table 20: TE0807-03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

Trenz shop TE0807 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings




Notes / Reference Document

PL_DCIN-0.34VTPS82085SIL / EN63A0QI data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN-0.34VTPS82085SIL / TPS51206 data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.34VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925
MGT clock absolute input voltage-0.51.3VXilinx document DS925

MGT Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,

"Enable"-signals on TPS82085SIL
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)




ROHM Semiconductor SML-P11 Series data sheet

Table 21: Module absolute maximum ratings

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN3.33.6VEN63A0QI / TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN3.33.6VTPS82085SIL / TPS51206PSQ data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC3.33.6VTPS82085SIL / TPS3106 data sheet
GT_DCDC3.33.6VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.33.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
PL bank reference voltage VREF pin-0.52VXilinx DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41


TPS3106 data sheet,

Table 22: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

See Xilinx datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips.

Physical Dimensions

All dimensions are given in millimeters.


Revision History

Hardware Revision History



PCN LinkDocumentation Link
2020-06-0503current available module revisionPCN-20200511TE0807-03
-02current available module revision-TE0807-02
-01first production release-TE0807-01

Table 23: Hardware revision history table

Document Change History

Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.





  • Correction on Power section
2021-06-10v.27John Hartfiel
  • correction number IOs in BD
2021-05-17v.26John Hartfiel
  • typo correction in DDR section
2021-05-03v.25Martin Rohrmüller
  • Updated to REV03



Antti Lukats

  • Corrected B2B include macro


v.22John Hartfiel
  • typo correction SI5345 I2C address
  • typo B2B Pin of CLK signals


v.20Ali Naseri
  • initial document

Table 24: Document change history