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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Key Features

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PetaLinux
SD
2x ETH
I2C
RTC

Revision History

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Date	Vivado	Project Built	Authors	Description
2017-09-11	2017.1	te0803-SK0803_zusys_SDSoC-vivado_2017.1-build_05_20170911131522	John Hartfiel	initial release

Release Notes and Know Issues

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Issues	Description	Workaround	To be fixed version
UBoot ETH PHY Address	PHY Address is not set correctly for UBoot	---	---
Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz"	This can be ignored, ETH works.

Requirements

Software

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Software	Version	Note
Vivado	2017.2	needed
SDK	2017.2	needed
PetaLinux	2017.2	needed

Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module Model	Board Part Short Name	PCB Revision Support	Notes
TE0728-03-1Q	03_1q	01,02,03
TE0728-04-1Q	04_1q	04

Design supports following carriers:

Carrier Model	Notes
TEB0728

Additional HW Requirements:

Additional Hardware	Notes
USB Cable for JTAG/UART
XMOD Programmer

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib	Vivado Project will be generated by TE Scripts
SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux	<design name>/os/petalinux	PetaLinux template with current configuration

Additional Sources

Type	Location	Notes

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

TE0728 Reference Design Download Area

Design Flow

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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

MIO Bank 501 Power is Carrier depends and set to 3.3V. Please check Settings, if you use a own carrier.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Programming

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Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

SD

Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

Open Serial Console (e.g. putty)
1. Speed: 115200
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
1. User Name: root
2. Password: root
You can use Linux shell now.
1. I2C 0 Bus type: i2cdetect -y -r 0
2. ETH0 works with udhcpc
3. ETH1 must be configured manually
  1. ifconfig eth1 up
  2. ifconfig eth1 <ip>
    Note for Ping test disable ETH0
4. RTC check: dmesg | grep rtc

System Design - Vivado

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Block Design

Public Docs > TE0728 Test Board > bd_test_board.png

PS Interfaces

Type	Note
DDR	---
QSPI	MIO
CAN1	MIO
ETH0	EMIO
ETH1	EMIO
SD0	MIO
UART1	MIO
I2C0	MIO
SPI1	MIO
GPIO	MIO/EMIO
TIMER0	EMIO

Constrains

Basic module constrains

#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

#############
#ETH0/ETH1
#####
#pwr_down
set_property PACKAGE_PIN L21 [get_ports {PHY_PD[0]}]
set_property PACKAGE_PIN R20 [get_ports {PHY_PD[1]}]
#rst_n
set_property PACKAGE_PIN M15 [get_ports {PHY_RSTN[0]}]
set_property PACKAGE_PIN R16 [get_ports {PHY_RSTN[1]}]
#io standard
set_property IOSTANDARD LVCMOS33 [get_ports {PHY*}]
set_property IOSTANDARD LVCMOS33 [get_ports mdio_*]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_*]
set_property IOSTANDARD LVCMOS33 [get_ports {MII_*}]
#pullup/down for PHY address 1
set_property PULLUP   true [get_ports MII_col]
set_property PULLDOWN true [get_ports {MII_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_rxd[3]}]
#pullup/down for PHY address 2
set_property PULLDOWN true [get_ports MII_1_col]
set_property PULLUP   true [get_ports {MII_1_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[3]}]

#############
#ETH0
#####
set_property PACKAGE_PIN M16 [get_ports mdio_ethernet_0_mdio_io]
set_property PACKAGE_PIN P16 [get_ports MDIO_ETHERNET_0_mdc]
set_property PACKAGE_PIN M22 [get_ports {MII_txd[3]}]
set_property PACKAGE_PIN K21 [get_ports {MII_txd[2]}]
set_property PACKAGE_PIN M17 [get_ports {MII_txd[1]}]
set_property PACKAGE_PIN J22 [get_ports {MII_txd[0]}]
set_property PACKAGE_PIN J20 [get_ports {MII_rxd[3]}]
set_property PACKAGE_PIN J18 [get_ports {MII_rxd[2]}]
set_property PACKAGE_PIN K18 [get_ports {MII_rxd[1]}]
set_property PACKAGE_PIN L17 [get_ports {MII_rxd[0]}]
set_property PACKAGE_PIN L16 [get_ports MII_col]
set_property PACKAGE_PIN N15 [get_ports MII_crs]
set_property PACKAGE_PIN L18 [get_ports MII_rx_clk]
set_property PACKAGE_PIN P15 [get_ports MII_rx_dv]
set_property PACKAGE_PIN P17 [get_ports MII_rx_er]
set_property PACKAGE_PIN K19 [get_ports MII_tx_clk]
set_property PACKAGE_PIN J21 [get_ports MII_tx_en]

#############
#ETH1
#####
set_property PACKAGE_PIN T16 [get_ports mdio_ethernet_1_mdio_io]
set_property PACKAGE_PIN T17 [get_ports MDIO_ETHERNET_1_mdc]
set_property PACKAGE_PIN R21 [get_ports {MII_1_txd[3]}]
set_property PACKAGE_PIN P22 [get_ports {MII_1_txd[2]}]
set_property PACKAGE_PIN P21 [get_ports {MII_1_txd[1]}]
set_property PACKAGE_PIN N22 [get_ports {MII_1_txd[0]}]
set_property PACKAGE_PIN T19 [get_ports {MII_1_rxd[3]}]
set_property PACKAGE_PIN T18 [get_ports {MII_1_rxd[2]}]
set_property PACKAGE_PIN R19 [get_ports {MII_1_rxd[1]}]
set_property PACKAGE_PIN R18 [get_ports {MII_1_rxd[0]}]
set_property PACKAGE_PIN P20 [get_ports MII_1_col]
set_property PACKAGE_PIN N18 [get_ports MII_1_crs]
set_property PACKAGE_PIN M19 [get_ports MII_1_rx_clk]
set_property PACKAGE_PIN N17 [get_ports MII_1_rx_dv]
set_property PACKAGE_PIN P18 [get_ports MII_1_rx_er]
set_property PACKAGE_PIN N19 [get_ports MII_1_tx_clk]
set_property PACKAGE_PIN M21 [get_ports MII_1_tx_en]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design - PetaLinux

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PetaLinux KICKstart

Description currently not available.

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};

/* ETH PHY */
&gem0 {
    phy-mode = "mii";
    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        // compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <1>;
    };
};

&gem1 {
    phy-mode = "mii";
    status = "okay";
    local-mac-address = [00 0a 35 00 1e 01];
        ethernet_phy1: ethernet-phy@1 {
        // compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <2>;
    };
};
/* RTC */
&i2c0 {
    rtc@56 {        // Real Time Clock
       compatible = "rv3029c2";
       reg = <0x56>;
   };
 
};

Kernel

Activate:

RTC_DRV_RV3029C2

Rootfs

Activate:

I2C-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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No additional software is needed.

SDSoC Design

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SDSoC Projects

Description currently not available.

SDSoC Platform

SDSoC Demo Examples

SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples

array_partition
burst_rw
custom_data_type
data_access_random
dependence_inter
direct_connect
dma_sg
dma_simple
full_array_2d
hello_vadd
lmem_2rw
loop_fusion
loop_perfect
loop_pipeline
loop_reorder
row_array_2d
shift_register
systolic_array
sys_port
wide_memory_rw
window_array_2d

There are 3 larger Linux demo projects demonstrating video processing with data I/O from file to file. Source code of these projects have been installed into this platform from the Xilinx SDSoC 2016.4 release:

file_io_manr_sobel
file_io_optical
file_io_sbm

These larger Linux demo projects demonstrate video processing with data I/O from file to file. Source code of these projects have been installed into this platform from demos present in the Xilinx SDSoC 2016.4 release.

Compilation steps in the SDSoC 2017.1 is identical to above described examples. File I/O demos support only the Linux target.

These three files use as an input larger video files. These files have to be present on the SD card as an input. Algorithms write output file to the SD card. These files can be visualized by YUV Player Deluxe and other players. To reduce size of the project, the video data files are not included.

Video input files can be found in the Xilinx SDSoC 2016.4 distribution:

<xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
<xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
<xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv

Array partition

This example shows how to use array partitioning to improve performance of a hardware function.

Key Concepts:

Hardware Function Optimization
Array Partitioning

Keywords:

#pragma HLS ARRAY_PARTITION
complete

Burst rw

This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.

Key Concepts:

Burst Access

Custom data type

This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.

Key Concepts:

Custom Data Type

Keywords:

struct
packed
aligned

Data access random

This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.

Key Concepts:

Data Access Random

Keywords:

#pragma HLS PIPELINE
#pragma SDS access_pattern(a:RANDOM, b:RANDOM)
#pragma SDS data copy

Dependence inter

This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.

Key Concepts:

Inter Dependence

Keywords:

DEPENDENCE
inter

Direct connect

This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.

Key Concepts:

Direct Connection
Multiple Accelerators

Keywords:

#pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)

Dma sg

This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.

Key Concepts:

Scatter Gather DMA

Keywords:

#pragma SDS access_parttern(a:SEQUENTIAL)
#pragma SDS data_mover(a:AXIDMA_SG)
#pragma SDS data copy

Dma simple

This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.

Key Concepts:

Simple DMA

Keywords:

#pragma SDS access_parttern(a:SEQUENTIAL)
#pragma SDS data_mover(a:AXIDMA_SIMPLE)
#pragma SDS data copy

Full array 2d

This is a simple example of accessing full data from 2D array.

Key Concepts:

2D data array access

Hello vadd

----------

This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.

Key Concepts:

- Loop Pipelining

Keywords:

- #pragma HLS PIPELINE

Lmem 2rw

This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.

Key Concepts:

Hardware Function Optimization
2port BRAM Utilization
Two read/write Local Memory

Keywords:

#pragma HLS UNROLL FACTOR=2

Loop fusion

This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.

Key Concepts:

Hardware Function Optimization
Loop Fusion
Loop Pipelining

Keywords:

#pragma HLS PIPELINE

Loop perfect

This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.

Key Concepts:

Loop perfect

Keywords:

#pragma HLS PIPELINE
#pragma HLS ARRAY_PARTITION

Loop pipeline

This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.

Key Concepts:

Loop Pipelining

Keywords:

#pragma HLS PIPELINE

Loop reorder

This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.

Key Concepts:

Hardware Function Optimization
Loop Reorder to Improve II

Keywords:

#pragma HLS PIPELINE
#pragma HLS ARRAY_PARTITION

Row array 2d

This is a simple example of accessing each row of data from 2D array.

Key Concepts:

Row of 2D data array access

Keywords:

hls::stream

Shift register

This example demonstrates how to shift values in each clock cycle.

Key Concepts:

Hardware Function Optimization
Shift Register
FIR

Keywords:

#pragma HLS ARRAY_PARTITION

Systolic array

This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.

Key Concepts:

Systolic Array

Keywords:

#pragma HLS PIPELINE
#pragma HLS ARRAY_PARTITION

Sys port

This is a simple example which demonstrates sys_port usage.

Key Concepts:

sys_port
memory interface
memory non-caching

Keywords:

#pragma SDS data sys_port
#pragms HLS PIPELINE
sds_alloc_non_cacheable

Wide memory rw

This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.

Key Concepts:

wide memory access
burst read and write
custom datatype

Keywords:

struct

Window array 2d

This is a simple example of accessing window of data from 2D array.

Key Concepts:

Window of 2D data array access

Keywords:

#pragma HLS DATAFLOW
#pragma HLS PIPELINE
#pragma HLS stream

File IO Video Processing

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.

Key Concepts:

Video processing from file to file
Direct connection of HW accelerated blocks

Select the "File IO Video Processing" template an compile for Linux target as project te22. Copy result to root of SD card. Copy also the input file input.yuv (82 944 000 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by comman ./te22.elf ./input.yuv 20 3 ./output.yuv

The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Dense Optical Flow

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.

Key Concept:s

Video processing from file to file
Direct connection of HW accelerated blocks
Top down methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

Select the "File IO Dense Optical Flow" template an compile for Linux target as project te23. Copy result to root of SD card. Copy also the input file route85_1920x1080.yuv (8 294 400 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te23.elf

The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Stereo Block Matching

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.

Key Concepts:

Video processing from file to file
Bottom Up methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

Select the "File IO Stereo Block Matching" template an compile for Linux target as project te24. Copy result to root of SD card. Copy also the input file desk_1280x720.yuv (1 843 200 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te24.elf

The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Date	Document Revision	Description
		Work in progress
2017-09-11	v.1	Initial release
	All

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

QSPI

SD

JTAG

Usage

Linux

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

FSBL

U-Boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

Kernel

Rootfs

Applications

startup

Additional Software

SDSoC Design

SDSoC Platform

SDSoC Demo Examples

Array partition

Burst rw

Custom data type

Data access random

Dependence inter

Direct connect

Dma sg

Dma simple

Full array 2d

Hello vadd

Lmem 2rw

Loop fusion

Loop perfect

Loop pipeline

Loop reorder

Row array 2d

Shift register

Systolic array

Sys port

Wide memory rw

Window array 2d

File IO Video Processing

File IO Dense Optical Flow

File IO Stereo Block Matching

Appx. A: Change History and Legal Notices

Document Change History

Legal Notices