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Table of Contents

Overview


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Refer to https://wiki.trenz-electronic.de/display/PD/TEBA0841+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEBA0841 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi-gigabit transceiver units of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 base-board.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBA0841-01 Block Diagram.

Main Components

    

Figure 2TE0706-02 Carrier Board.

  1. Samtec Razor Beam™ LSHM-150 B2B connector, JB1
  2. Samtec Razor Beam™ LSHM-150 B2B connector, JB3
  3. Samtec Razor Beam™ LSHM-130 B2B connector, JB2
  4. 6-pin header J26, for selecting PL I/O-bank voltage
  5. 6-pin header J27, for selecting PL I/O-bank voltage
  6. Micro USB2.0 Type B Connector J12 (Device or OTG mode)
  7. JTAG/UART header, JX1 ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  8. User LED D1 (green)
  9. User LED D2 (red)
  10. SFP+ Connector, J1
  11. 50-pin header soldering-pads J17, for access to PL I/O-bank pins (LVDS-pairs possible)
  12. 50-pin header soldering-pads J20, for access to PL I/O-bank pins (LVDS-pairs possible)
  13. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  14. 10-pin header soldering-pads J4, for access to SoM's SDIO-port, if available

Initial Delivery State

Board is shipped in following configuration:

Different delivery configurations are available upon request.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TEBA0841 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

B2B ConnectorInterfacesCount of I/O'sNotes
JB1User I/O42 single ended or 21 differential-
SD IO6-
MIO8-
SoM control signals1'BOOTMODE'
JB2MGT lanes8 differential pairs, 4 lanes-
MGT reference input clock1 differential pair
USB2.0 (OTG and device mode)4-
JB2User I/O42 single ended 21 differential--
JTAG4-
Red user LED1-

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Pin Header

The TEBA0841 Carrier Board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

On-board Pin Header
Control Signals and InterfacesCount of I/O'sNotes
J17User I/O42 single ended or 21 differential-
J20

User I/O

42 single ended or 21 differential-
J3JTAG4-
SoM control signals2'RESIN', 'BOOTMODE'
MGT reference input clock1 differential pairAC decoupled on-board (100 nF capacitor)
MIO2user IO (configurable as UART for example)
J4SD IO63.3V and 1.8V voltage level available on header

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

SFP+ Connector

On the TEBA0841 carrier board is a SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JB2, the control-lines are connected to B2B connector JB1 and are assigned to MIO-bank pins of the mounted SoM.

The pin-assignment of the SFP connector is in detail as fellows:


SFP+ pinPin Schematic NameB2BFPGA DirectionDescriptionNote
Transmit Data + (pin 18)MGT_TX3_PJB2-26OutputSFP+ transmit data differential pair

-
Transmit Data - (pin 19)MGT_TX3_NJB2-28Output-
Receive Data + (pin 13)MGT_RX3_PJB2-25InputSFP+ receive data differential pair

-
Receive Data - (pin 12)MGT_RX3_NJB2-27Input-
Receive Fault (pin 2)MIO10JB1-96InputFault / Normal OperationHigh active logic
Receive disable (pin 3) 1)SFP0_TX_DISnot connectedOutputSFP Enabled / DisabledLow active logic
MOD-DEF2 (pin 4)MIO13JB1-98InputModule present / not presentLow active logic
MOD-DEF1 (pin 5)MIO12JB1-100Output2-wire Serial Interface clock3.3V pull-up on-board
MOD-DEF0 (pin 6)MIO11JB1-94BiDir2-wire Serial Interface data3.3V pull-up on-board
RS0 (pin 7)SFP0_RS0not connectedOutputFull RX bandwidthLow active logic
LOS (pin 8)MIO0JB1-88InputLoss of receiver signalHigh active logic
RS1 (pin 9)SFP0_RS1not connectedOutputReduced RX bandwidthLow active logic

Table 1: SFP+ connector pin-assignment.

1) Important: For proper operation, a wire patch to GND is done at recently delivered boards. Connect to GND, if not done. See PCB drawing below:



Figure 3: PCB wire patch for SFP+ connector.

Looped-backed MGT-Lanes on B2B Connector JB1 and JB2


The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification. 


The MGT lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:


MGT LaneB2B TX Differential PairB2B RX Differential PairB2B Pins Bridged
MGT-lane 0

JB2-8 (MGT_TX0_N)

JB2-10 (MGT_TX0_P)

JB2-7 (MGT_RX0_N)

JB2-9 (MGT_RX0_P)

JB2-7 to JB2-8

JB2-9 to JB2-10

MGT-lane 1

JB2-14 (MGT_TX1_N)

JB2-16 (MGT_TX1_P)

JB2-13 (MGT_RX1_N)

JB2-15 (MGT_RX1_P)

JB2-13 to JB2-14

JB2-15 to JB2-16

MGT-lane 2

JB2-20 (MGT_TX2_N)

JB2-22 (MGT_TX2_P)

JB2-19 (MGT_RX2_N)

JB2-21 (MGT_RX2_P)

JB2-19 to JB2-20

JB2-21 to JB2-22

MGT-lane 7

JB1-3 (MGT_TX7_P)

JB1-5 (MGT_TX7_N)

JB1-9 (MGT_RX7_P)

JB1-11 (MGT_RX7_N)

JB1-3 to JB1-9

JB1-5 to JB1-11

MGT-lane 6

JB1-15 (MGT_TX6_P)

JB1-17 (MGT_TX6_N)

JB1-21 (MGT_RX6_P)

JB1-23 (MGT_RX6_N)

JB1-15 to JB1-21

JB1-17 to JB1-23

Table 2: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.


Note: The mounted TE 4 x 5 SoMs have different schematic net-names of the differential signaling pairs of the MGT-lanes. See Schematic of the particular SoM.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

JTAG Signal

B2B Connector Pin

XMOD Header JX1Pin Header J3Note
TCKJB3-100JX1-4J3-4-
TDIJB3-96JX1-10J3-10-
TDOJB3-98JX1-8J3-8-
TMSJB3-94JX1-12J3-12-

Table 3: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3Note
MIO14JB1-91JX1-7J3-7UART-RX (receive line)
MIO15JB1-86JX1-3J3-3UART-TX (transmit line)

Table 4: UART interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

SD IO Signal Schematic NameB2BPin Header J4Note
SD_DAT0JB1-24J4-8SD IO data
SD_DAT1JB1-22J4-10SD IO data
SD_DAT2JB1-20J4-9SD IO data
SD_DAT3JB1-18J4-7SD IO data
SD_CLKJB1-28J4-4SD IO clock
SD_CMDJB1-26J4-3SD IO command

Table 6: SD IO interface signals.

USB2.0 Interface

TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.

Following table gives an overview of the USB2.0 interface signals:

USB2.0 Signal Schematic NameB2BConnected toNote
OTG_N

JB2-48

J10-2USB2.0 data
OTG_PJB2-50J10-3USB2.0 data
OTG-IDJB2-52J10-4Ground this pin for A-Device (host),  left floating this pin for B-Device (peripheral).
USB-VBUSJB2-56J10-1USB supply voltage for Host mode. Not supplied by the Carrier Board.

Table 7: USB2.0 interface signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1 and pin header J3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal.

So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:

Pin Schematic NameXMOD Header JX1 PinHeader J3 PinB2BNote
TCKC (pin 4)4JB3-100-
TDOD (pin 8)8JB3-98-
TDIF (pin 10)10JB3-96-
TMSH (pin 12)12JB3-94-
MIO15A (pin 3)3JB1-86UART-TX (transmit line)
MIO14B (pin 7)7JB1-91UART-RX (receive line)
BOOTMODEE (pin 9)9JB1-90usually 'JTAGSEL' on TE 4 x 5 SoMs
RESING (pin 11)11JB3-17SoM Reset pin
CLK0_N-15JB2-32AC decoupled on-board (100 nF capacitor)
CLK0_P-16JB2-34AC decoupled on-board (100 nF capacitor)

Table 10: JTAG/UART header signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the DIP-switch with the setting:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4OFF

Table 11: XMOD adapter board DIP-switch positions for voltage configuration.

Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

LED ColorPin Schematic NameB2B ConnectorDescription and Notes
D1GreenMIO9JB1-92available to user
D2RedRLEDJB3-90available to user

Figure 3: On-board LEDs

VCCIO Selection Jumper

On the TEBA0841 carrier board different VCCIO configurations can be selected by the jumper J26 and J27.

TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on their B2B connectors, which will be fed with I/O voltage from base-board.

Base-board PL-bank I/O Voltages

B2B PinsStandard Assignment of PL-bank I/O Voltages on TE 4x5 Modules
VCCIOAJB1-10, JB1-12VCCIOA (JM1-9, JM1-11)
VCCIODJB2-8, JB2-10VCCIOD (JM2-7, JM2-9)

Table 5: Base-board PL-bank I/O voltages VCCIOA and VCCIOD

Note: The corresponding PL-bank I/O voltages of the 4 x 5 SoM to the selectable base-board voltages VCCIOA and VCCIOD are depending on the mounted 4 x 5 SoM and varying in order of the used model.

Refer to the SoM's schematic for information about the specific pin assignments on module's B2B-connectors regarding the PL-bank I/O voltages and to the 4 x 5 Module integration Guide for VCCIO voltage options.

Following table describes how to configure the base-board supply-voltages by jumpers:

Base-board PL-bank I/O Voltages
vs Voltage Levels

VCCIOAVCCIOD
1.8VJ26: 1-2J27: 1-2
2.5VJ26: 3-4J27: 3-4
3.3VJ26: 5-6J27: 5-6

Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
3.3VTBD*

Table 14: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.

Power Supply

Power supply with minimum current capability of 3A at 3.3V for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

The external power-supply can be connected to the board by the following pins:

Connector3.3V pinGND pin
JX1

JX1-5, JX1-6,

JX1-1, JX1-2
J3J3-5, J3-6J3-1, J3-2
J4J4-5J4-1, J4-2
J20J20-5, J20-46J20-1 , J20-2 , J20-49 , J20-50
J17J17-5, J17-46J17-1 , J17-2 , J17-49 , J17-50

Table 4: Connector pins capable for external 3.3V power supply

Power Distribution Dependencies

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM2-10 and JM2-12, meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram shows the distribution of the external input voltage of nominal 3.3V to the components:


Figure 5: Board power distribution diagram.

Power Rails

The voltage direction of the power rails is from board and on-board connectors' view:

Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

3.3V

Out

2, 4, 6, 14, 16

3.3V module supply voltage
VCCIOAOut10, 12PL IO-bank VCCIO
M1.8VOUTIn401.8V module output voltage
JB2

1.8V

Out

2, 4

1.8V module supply voltage
VCCIODOut8, 10PL IO-bank VCCIO
3.3V_OUTIn9, 113.3V module output voltage
JB3USB-VBUSOut56USB Host supply voltage

Table 15: Power pin description of B2B module connector.


On-board Pin Header DesignatorVCC / VCCIODirectionPinsNotes
J5

3.3V

Out

6, 45

3.3V module supply voltage
M3.3VOUTIn5, 463.3V module output voltage
J6

VCCIOA

Out

B32

PL IO-bank VCCIO
VCCIOCOutB1PL IO-bank VCCIO
M3.3VOUTInC323.3V module output voltage
3.3VOutC313.3V module supply voltage
5VINInA1, A2Carrier Board supply power

Table 16: Power Pin description of on-board connector.


Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J10VCCIOAOut2-
1.8VOut1-
M3.3VOUTOut3-
J11

VCCIOB

Out2-
1.8VOut1-
M3.3VOUTOut3-
J12VCCIOCOut2-
1.8VOut1-
M3.3VOUTOut3-

Table 17: Power Pin description of VCCIO selection jumper pin header.


Main Power Jack and Pins DesignatorVCC / VCCIODirectionPinsNotes
J15VINIn

-

-
J65VINInA1, A2'5VIN' power supply to the Carrier Board as alternative to J1
J9VBATIn1Attention: Pin 2 connected to ground. VBAT voltage connected on this pin cause short-circuit.

Table 18: Main Power jack and pins description.


Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J7 / J8USB-VBUSOut1USB2.0 Type A socket / Micro USB2.0 B socket
J4M3.3VOUTOut4MikroSD Card socket VDD

Table 19: Power pin description of peripheral connector.


XMOD Header DesignatorVCC / VCCIODirectionPinsNotes
JX13.3V-5not connected
VIOOut6connected to 'VCCJTAG' (pin JB2-92)

Table 20: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

5VIN supply voltage

 -0.3 7

V

MP5010A, EN6347QI, EN5311QI data sheet

Storage temperature

 -55

+85

°C

Marvell 88E1512 data sheet

Table 22: Module absolute maximum ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
5VIN supply voltage 4.755.25 VUSB2.0 specification concerning 'VBUS' voltage
Operating temperature -40+85°C-

Table 23: Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

The TE0706 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

 All dimensions are given in millimeters.


Figure 6: Board physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2016-06-28

01

  • Prototypes
 -TE0706-01
-02
  • First Production Release
  • Refer to Changes list in Schematic

    for further details in changes to REV01

-TE0706-02

Table 24: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


Figure 7: Board hardware revision number.

Document Change History

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Date

Revision

Contributors

Description



Ali Naseri
  • TRM revision to new common style

2017-07-06

v.52
Ali Naseri, Jan Kumann
  • Hardware revision 02 specific changes.
2017-01-06v.1Ali Naseri
  • initial document to board revision 02

Table 25: Document change history.

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