Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Create DrawIO object here: Attention if you copy from other page, use   image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

       

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

    •  

      Example Comment 1 2

       

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 2019.2
• PetaLinux/Ubuntu/Debian
• SD
• ETH (use EEPROM MAC)
• USB
• I2C
• RTC
• VIO PHY LED
• HDMI
• FSBL for EEPROM MAC and CPLD access and HDMI DMA
• TE0701 (only supported)

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if  issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of software which was used to generate the design

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  •  

    File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Specification-Files *.xsa Exported Vivado Hardware Specification for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

     

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequ:...
      

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design

#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

#
# If Bank 34 is not 2.5V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS25 [get_ports PL_pin*]

#
# TE0701 I2C Bus
#
set_property PACKAGE_PIN W20 [get_ports IIC_0_scl_io]
set_property PACKAGE_PIN W21 [get_ports IIC_0_sda_io]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_0_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_0_sda_io]

#
# ADV7511 Interface
#
set_property PACKAGE_PIN N20 [get_ports hdmi_out_clk]
set_property PACKAGE_PIN N19 [get_ports hdmi_out_de]
set_property PACKAGE_PIN R19 [get_ports hdmi_out_hsync]
set_property PACKAGE_PIN T19 [get_ports hdmi_out_vsync]
set_property PACKAGE_PIN T18 [get_ports {hdmi_out_data[0]}]
set_property PACKAGE_PIN R18 [get_ports {hdmi_out_data[1]}]
set_property PACKAGE_PIN R21 [get_ports {hdmi_out_data[2]}]
set_property PACKAGE_PIN R20 [get_ports {hdmi_out_data[3]}]
set_property PACKAGE_PIN M22 [get_ports {hdmi_out_data[4]}]
set_property PACKAGE_PIN K21 [get_ports {hdmi_out_data[5]}]
set_property PACKAGE_PIN M21 [get_ports {hdmi_out_data[6]}]
set_property PACKAGE_PIN J20 [get_ports {hdmi_out_data[7]}]
set_property PACKAGE_PIN T17 [get_ports {hdmi_out_data[8]}]
set_property PACKAGE_PIN J22 [get_ports {hdmi_out_data[9]}]
set_property PACKAGE_PIN T16 [get_ports {hdmi_out_data[10]}]
set_property PACKAGE_PIN J21 [get_ports {hdmi_out_data[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports hdmi_*]

set_property PACKAGE_PIN AB16 [get_ports {cec_clk[0]}]
set_property PACKAGE_PIN AB17 [get_ports {ct_hpd[0]}]
set_property PACKAGE_PIN AA16 [get_ports {ls_oe[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cec_clk[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ct_hpd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ls_oe[0]}]

• optional chapter separate

• sections for different apps

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
• Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

#include <configs/platform-auto.h>


#define UBOOT_ENV_MAGIC 0xCAFEBABE
#define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00
#define UBOOT_ENV_ADDR 0xFFFFFC04


#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"


/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Dependencies for ENV to be stored in EEPROM. Ensure environment fits in eeprom size*/
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
#define CONFIG_SYS_I2C_EEPROM_ADDR             0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
#define CONFIG_SYS_EEPROM_SIZE                 1024 /* Bytes */
#define CONFIG_SYS_I2C_MUX_ADDR                0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_SEL          0x4
#endif


#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"

/include/ "system-conf.dtsi"
/ {
};
 
 
/ {
    memory {    // Reduce memory for framebuffers
        device_type = "memory";
        reg = <0x0 0x3FC00000>;  // Reduce memory for 1GB assembly variant
      //  reg = <0x0 0x1FC00000>;  // Reduce memory for 1GB assembly variant
      //  reg = <0x0 0x0FC00000>;  // Reduce memory for 1GB assembly variant
    };
 
 
    framebuffer0: framebuffer@0x3FC00000 {      // HDMI out
        compatible = "simple-framebuffer";
        reg = <0x3FC00000 (1280 * 720 * 4)>;    // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };
 
/*
    framebuffer0: framebuffer@0x1FC00000 {      // HDMI out
        compatible = "simple-framebuffer";
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };
*/
/*
    framebuffer0: framebuffer@0x0FC00000 {      // HDMI out
        compatible = "simple-framebuffer";
        reg = <0x0FC00000 (1280 * 720 * 4)>;    // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };
*/
};

&axi_vdma_0 {
   status = "disabled";
};
 
&v_tc_0 {
    //xilinx-vtc: probe of 43c20000.v_tc failed with error -2
    status = "disabled";
};

 
/* default */
 
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
 
 
/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};
 
/* USB PHY */
 
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
 
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};
 
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
 
    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
        gpio-controller;
    };
 
    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
        gpio-controller;
    };
 
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;
    };
};

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports