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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
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Date | Vivado | Project Built | Authors | Description |
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2017.4 | John Hartfiel | |||
2017-11-10 | 2017.2 | te0715-test_board-vivado_2017.2-build_05_20171110134232.zip te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip | John Hartfiel |
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2017-10-19 | 2017.2 | te0715-test_board-vivado_2017.2-build_04_20171019141808.zip te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip | John Hartfiel |
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2017-09-22 | 2017.2 | te0715-test_board-vivado_2017.2-build_02_20170927143412.zip te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip | John Hartfiel |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Short Name | PCB Revision Support | DDR | QSPI Flash | Notes |
---|---|---|---|---|---|
te0715-03-15-1c | 03_15_1c | REV01,02,03 | 1GB | 32 | |
te0715-03-15-1i | 03_15_1i | REV01,02,03 | 1GB | 32 | |
te0715-03-15-2i | 03_15_2i | REV01,02,03 | 1GB | 32 | |
te0715-03-30-1c | 03_30_1c | REV01,02,03 | 1GB | 32 | |
te0715-03-30-1i | 03_30_1i | REV01,02,03 | 1GB | 32 | |
te0715-03-30-3e | 03_30_3e | REV01,02,03 | 1GB | 32 | |
te0715-04-15-1c | 04_15_1c | REV04 | 1GB_L | 32 | |
te0715-04-15-1i | 04_15_1i | REV04 | 1GB_L | 32 | |
te0715-04-15-2i | 04_15_2i | REV04 | 1GB_L | 32 | |
te0715-04-30-1c | 04_30_1c | REV04 | 1GB_L | 32 | |
te0715-04-30-1i | 04_30_1i | REV04 | 1GB_L | 32 | |
te0715-04-30-3e | 04_30_3e | REV04 | 1GB_L | 32 | |
te0715-04-12s-1c | 12s | REV04 | 1GB_L | 32 |
Design supports following carriers:
Carrier Model | Notes |
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TE0701 | |
TE0703 | used as reference carrier |
TE0705 | |
TE0706 | |
TEBA0841 |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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For general structure and of the reference design, see Project Delivery
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
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--- | --- | --- |
<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
Only on ZIP file with Prebuilt content.
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch. TE0715-0x-30-xx only: HP IO Banks max power supply voltage is 1.8V. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used on this Example.
Not used on this Example.
MGT Reference CLK Counter:
MGT CLK is configured to 125MHz by default, FCLK is not configured by default.
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Activated interfaces:
Type | Note |
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DDR | --- |
QSPI | MIO |
I2C0 | EMIO- NC |
I2C1 | MIO |
UART0 | MIO |
GPIO | MIO |
SD0 | MIO |
USB0 | MIO |
ETH0 | MIO |
TTC | EMIO |
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]] |
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For SDK project creation, follow instructions from:
TE modified 2017.2 FSBL
Changes:
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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For PetaLinux installation and project creation, follow instructions from:
No changes.
No changes.
/include/ "system-conf.dtsi" / { }; /* default */ /* ETH PHY */ &gem0 { status = "okay"; ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C */ // i2c PLL: 0x70, i2c eeprom: 0x50 &i2c1 { rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Activate:
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
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Download ClockBuilder Desktop for SI5338
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | Authors | Description |
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| Release 2017.3 - working in process | ||
2017-11-10 | v.22 | John Hartfiel |
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2017-10-19 | v.21 | John Hartfiel |
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2017-10-19 | v.20 | John Hartfiel |
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2017-10-06 | v.18 | John Hartfiel |
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2017-10-02 | v.14 | John Hartfiel |
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2017-09-28 | v.13 | John Hartfiel | Release 2017.2 |
2017-09-11 | v.1 | Initial release | |
All |