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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
Zynq PS Design with Linux Example.
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Date | Vivado | Project Built | Authors | Description |
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2018-01-31 | 2017.4 | te0726-test_board-vivado_2017.4-build_05_20180131115412.zip te0726-test_board_noprebuilt-vivado_2017.4-build_05_20180131115451.zip | John Hartfiel | initial release 2017.4 |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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te0726-01 | 01 | REV01 | 128MB LPDDR2 | 16MB | ||
te0726-03r | r | REV02, REV03 | 128MB DDR3L | 16MB | ||
te0726-03m | m | REV02, REV03 | 512MB DDR3L | 16MB | ||
te0726-03-07s-1c | 7s | REV03 | 512MB DDR3L | 16MB |
Design supports following carriers:
Carrier Model | Notes |
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--- |
Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable | Connect to USB2 or better USB3 Hub for proper power supply over USB |
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For general structure and of the reference design, see Project Delivery
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Since Vivado 2017.4 FSBL is needed to program QSPI. (2017.2 works without FSBL). Xilinx mini-uboot starts with this FSBL configuration but needs QSPI FB CLK enabled on PS. On TE0726, this MIO is used for UART, so special design is need to generate this FSBL. This reference design contains a prebuilt FSBL for QSPI programming (zynqmp_fsbl_flash), so there is normally no need to regenerate this special FSBL. In case of generate this by yourself following steps are needed
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)
Not used on this Example.
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Type | Note |
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DDR | --- |
QSPI | MIO |
USB0 | MIO, ETH over USB |
SD1 | MIO |
UART1 | MIO |
I2C1 | MIO |
GPIO | MIO |
USB RST | MIO |
TTC0..1 | MIO |
WDT | MIO |
# # Common BITGEN related settings for TE0726 # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
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For SDK project creation, follow instructions from:
Xilinx default FSBL
TE modified 2017.4 FSBL
Changes:
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Hello World App in endless loop.
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For PetaLinux installation and project creation, follow instructions from:
No changes.
No changes.
/include/ "system-conf.dtsi" / { }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C1 */ &i2c1 { #address-cells = <1>; #size-cells = <0>; i2cmux0: i2cmux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c1@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; id_eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c1@1 { // Display Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c1@2 { // HDMI Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c1@3 { // Camera Interface Connector #address-cells = <1>; #size-cells = <0>; reg = <3>; }; }; }; |
Activate:
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
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No additional software is needed
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2018-01-31 | v.1 |
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