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Zynq PS Design with Linux Example.
Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2020.2
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • Special FSBL for QSPI programming

Revision History

DateVivadoProject BuiltAuthorsDescription
Mohsen Chamanbaz
  • 0001-QSPI-s25fl127_8-2020_2.patch for restart
  • Added Ethernet interface

Mohsen Chamanbaz
  • 2020.2 release
  • Without Etherner interface
Mohsen Chamanbaz/John Hartfiel
  • changes FSBL flash
Mohsen Chamanbaz/John Hartfiel
  • script update
Mohsen Chamanbaz
  • Update to 19.2
  • Vitis support
  • prebuilt binary export on selection guide
Mohsen Chamanbaz
  • FSBL update to18.3
  • additional linux apps
John Hartfiel
  • Changed SDK Notes on FSBL template fro Flash programming
John Hartfiel
  • change note for REV01
  • no design changes
John Hartfiel
  • correction netboot offset for 128MB variant
John Hartfiel
  • correction PS REFCLK for 01 variant
John Hartfiel
  • initial release 2017.4
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
Flash Programming failed with 19.2Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 )2019.2 version
  • Option1:
    • In case Flash is empty, use fsbl_flash on programming GUI 
    • In case Flash is programmed use normal fsbl on programming GUI
  • Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
FSBL/ Kernel
Vivado 2020.2
Petalinux does not restart after first bootinguse 0001-QSPI-s25fl127_8-2020_2.patch from
Known Issues



Vitis2020.2needed, Vivado is included into Vitis installation


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes


te0726-03rr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
TE0726-03RJr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
TE0726-03-41C74-Rr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
TE0726-03-41C64-A m_512MBREV03,REV02512MB16MBNANALPDDR3   
Hardware Modules

Design supports following carriers:

Carrier ModelNotes
Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB CableConnect to USB2 or better USB3 Hub for proper power over USB
Additional Hardware


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes<design name>/misc/sd/Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    • (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  8. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  9. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

      Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power module (TE0726 can be powered via JTAG USB or external)
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0820 (optional)

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  4. Copy image.ub and boot.scr on SD or USB
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    • Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
  5. Insert SD-Card


Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Insert SD Card with image.ub

    Note: See TRM of the board, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    petalinux login: root
    Password: root

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 0 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
  4. Option Features
    1. Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    2. scripts
      • add script on SD, content will be load automatically on startup (template included in ./misc/SD)

System Design - Vivado

Block Design

Block Design

PS Interfaces

PS Interfaces


Basic module constrains

# Common BITGEN related settings for TE0726
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Software Design - Vitis

For SDK project creation, follow instructions from:



Template location: ./sw_lib/sw_apps/


TE modified 2020.2 FSBL


  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • ---


TE modified 2020.2 FSBL


  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


Hello TE0726 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description


For 512MB variant:

  • No changes

For 64MB variant only:


For 128MB variant only:



Start with petalinux-config -c u-boot



  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

Device Tree

/include/ "system-conf.dtsi"
/ {
/* USB PHY */
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
/* I2C1 */
&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;
    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;
        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;


Start with petalinux-config -c kernel






  • CONFIG_USB_NET_AX88179_178A=y


  • # CONFIG_USB_NET_CDC_EEM is not set



  • # CONFIG_USB_NET_CDC_MBIM is not set

  • # CONFIG_USB_NET_DM9601 is not set

  • # CONFIG_USB_NET_SR9700 is not set

  • # CONFIG_USB_NET_SR9800 is not set

  • # CONFIG_USB_NET_SMSC75XX is not set


  • # CONFIG_USB_NET_GL620A is not set


  • # CONFIG_USB_NET_PLUSB is not set

  • # CONFIG_USB_NET_MCS7830 is not set

  • # CONFIG_USB_NET_RNDIS_HOST is not set



  • # CONFIG_USB_ALI_M5632 is not set

  • # CONFIG_USB_AN2720 is not set



  • # CONFIG_USB_EPSON2888 is not set

  • # CONFIG_USB_KC2190 is not set


  • # CONFIG_USB_NET_CX82310_ETH is not set

  • # CONFIG_USB_NET_KALMIA is not set

  • # CONFIG_USB_NET_QMI_WWAN is not set

  • # CONFIG_USB_NET_INT51X1 is not set

  • # CONFIG_USB_SIERRA_NET is not set

  • # CONFIG_USB_VL600 is not set

  • # CONFIG_USB_NET_CH9200 is not set

  • # CONFIG_USB_NET_AQC111 is not set


  • # CONFIG_USBIP_VHCI_HCD is not set

  • # CONFIG_USBIP_HOST is not set

  • # CONFIG_USBIP_VUDC is not set

  • # CONFIG_USBIP_DEBUG is not set

Change linux-xlnx_%.bbappend:


SRC_URI += "file://devtool-fragment.cfg \
            file://0001-QSPI-s25fl127_8-2020_2.patch \
  • Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"


Start with petalinux-config -c rootfs


  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils = y
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y



Script App to load from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files


Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision



  • 2020.2 release
2020-06-23v.17John Hartfiel
  • typo


v.16John Hartfiel
  • Design update
  • Programming issue note
2020-03-25v.14John Hartfiel
  • script update
2020-02-19v.13Mohsen Chamanbaz
  • 2019.2 release
  • docu update



John Hartfiel

  • 2018.3 release
2018-07-13v.11John Hartfiel
  • 2018.2 release


v.9John Hartfiel
  • bugfix design for 128MB variant


v.8John Hartfiel
  • Link update
  • remove typo
2018-02-16v.6John Hartfiel
  • Design update
2018-02-09v.5John Hartfiel
  • 2017.4 release
Document change history.

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