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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.
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Date | Vivado | Project Built | Authors | Description |
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2018.01.09 | 2017.4 | te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip te0720-test_board-vivado_2017.4-build_02_20180109121300.zip | John Hartfiel |
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2017-11-27 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip te0720-test_board-vivado_2017.2-build_05_20171127153006.zip | John Hartfiel |
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2017-11-20 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip | John Hartfiel |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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te0720-03-2if | 2if | REV02, REV03 | 1GB | 32 | ||
te0720-03-2ifc3 | 2if | REV02, REV03 | 1GB | 32 | 2.5 mm connector | |
te0720-03-2ifc8 | 2if | REV02, REV03 | 1GB | 32 | 32GB eMMC |
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te0720-03-1qf | 1qf | REV02, REV03 | 1GB | 32 | ||
te0720-03-1cf | 1cf | REV02, REV03 | 1GB | 32 | ||
te0720-03-1cfa | 1cf | REV02, REV03 | 1GB | 32 | 8GB eMMC | |
te0720-03-2ef | 2ef | REV02, REV03 | 1GB | 32 | ||
te0720-03-1cr | 1cr | REV02, REV03 | 256MB | 32 | without eMMC | |
te0720-03-l1if | l1if | REV02, REV03 | 512MB (L) | 32 | ||
te0720-03-14s-1c | 14s | REV02, REV03 | 1GB (L) | 32 |
Design supports following carriers:
Carrier Model | Notes |
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TE0701 |
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TE0703 |
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TE0705 |
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TE0706 |
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TEBA0841 |
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Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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For general structure and of the reference design, see Project Delivery
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
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Not used on this Example.
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
PHY LED:
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Type | Note |
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DDR | --- |
QSPI | MIO |
ETH0 | MIO |
USB0 | MIO |
SD0 | MIO |
SD1 | MIO |
UART0 | MIO |
UART1 | MIO |
I2C0 | MIO |
I2C1 | EMIO |
GPIO | MIO |
TTC | EMIO |
# # Common BITGEN related settings for TE0720 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design |
# set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
# # Constraints for System controller support logic # set_property PACKAGE_PIN K16 [get_ports PL_pin_K16] set_property PACKAGE_PIN K19 [get_ports PL_pin_K19] set_property PACKAGE_PIN K20 [get_ports PL_pin_K20] set_property PACKAGE_PIN L16 [get_ports PL_pin_L16] set_property PACKAGE_PIN M15 [get_ports PL_pin_M15] set_property PACKAGE_PIN N15 [get_ports PL_pin_N15] set_property PACKAGE_PIN N22 [get_ports PL_pin_N22] set_property PACKAGE_PIN P16 [get_ports PL_pin_P16] set_property PACKAGE_PIN P22 [get_ports PL_pin_P22] # # If Bank 34 is not 3.3V Powered need change the IOSTANDARD # set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19] set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
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For SDK project creation, follow instructions from:
TE modified 2017.4 FSBL
Functions:
Changes:
TE modified 2017.4 FSBL
Changes:
Hello World App in Endless loop.
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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For PetaLinux installation and project creation, follow instructions from:
#include <configs/platform-auto.h> #define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp" |
/include/ "system-conf.dtsi" / { }; /* default */ /* Flash */ &qspi { flash0: flash@0 { compatible = "w25q256"; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x20>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Activate:
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
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No additional software is needed.
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Date | Document Revision | Authors | Description |
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2018-01-09 | v.16 | John Hartfiel |
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2017-11-27 | v.14 | John Hartfiel |
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2017-11-22 | v.12 | John Hartfiel |
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2017-11-22 | v.11 | John Hartfiel |
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2017-11-20 | v.1 |
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