<!--
Template Revision 1.3
Basic Notes
 - export PDF to download, if vivado revision is changed!
 - Template is for different design and SDSoC and examples, remove unused or wrong description!
 -->

Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Table of contents

<!--
General Design description
 -->

<!--
Add Basic Key Features of the design (should be tested)
 -->

• PetaLinux
• SD
• ETH
• USB
• I2C
• Special FSBL for QSPI programming

<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

<!--
- add known Design issues and general Notes for the current revision
 -->

<!--
Add needed external Software
   -->

<!--
Hardware Support
   -->

<!--
Remove unused content
  -->

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

<!--
Basic Design Steps
Add/ Remove project specific 
  -->

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Since Vivado 2017.4 FSBL is needed to program QSPI. (2017.2 works without FSBL). Xilinx mini-uboot starts with this FSBL configuration but needs QSPI FB CLK enabled on PS. On TE0726, this MIO is used for UART, so special design is need to generate this FSBL.

This reference design contains a prebuilt FSBL for QSPI programming (zynqmp_fsbl_flash), so there is normally no need to regenerate this special FSBL. In case of generate this by yourself following steps are needed

1. Create new default reference design
   1. Open PS and enable QSPI FB CLK
   2. Set UART to MIO 52 .. 53
   3. Create Bitfile
   4. Start SDK with with TE Scripts on Vivado TCL: TE::sw_run_sdk
2. ON SDK use zynqmp_fsbl_flash template.
   Important "zynqmp_fsbl_flash" FSBL can be only used on QSPI Flash Programming setup on Vivado or SDK Menu!

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Check Module and Carrier TRMs for proper HW configuration before you try any design.

<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

<!--
optional chapter
separate sections for different apps
  -->

<!--
optional chapter
Add "No changes." or "Activate: and add List"
   -->

/include/ "system-conf.dtsi"
/ {
};


/* USB PHY */

/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* I2C1 */

&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;

    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;


        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;

            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
            };

        };
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
    };

};

<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
  -->