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Overview

The Trenz Electronic TEC0850 board is an industrial-grade CompactPCI card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide databus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all on-board voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI backplane connectors.

Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

Key Features

• Zynq UltraScale+ MPSoC ZU15

• Front side interface connectors
  • RJ-45 GbE Ethernet interface
  • Elbow Socket with 4x on-board 8bit DAC output
  • MicroSD Card connector
  • USB2 and USB3 to FIFO bridge connector
  • 4x status LEDs
• 4 CompactPCI slots for backplane connection (3U form factor)
  • 24 GTH lanes
  • 4 PS GTR lanes
  • USB2 interface
  • 64 Zynq PL HP I/O's
  • 8x PLL clock input
  • JTAG, I²C and 7 user I/O's to MAX10 FPGA

• 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

• Dual parallel QSPI Flash (bootable), 512 MByte maximum

• 26-pin header with 20 Zynq PL HD I/O's
• 3-pin header with 2 MAX10 FPGA I/O's
• System Controller (Altera MAX10 FPGA SoC)
  • Power Sequencing
  • System management and control for MPSoC and on-board peripherals
• Si5345 programmable 10 output PLL clock generator
• Si53340 Quad PLL clock generator
• 2x 4bit DIP switches
• 1x user push button
• Zynq MPSoC cooling FAN connector
• On-board high-efficiency DC-DC converters

Block Diagram

Main Components

1. GbE RJ-45 MagJack, J7
2. DAC output 5-pin elbow receptacle socket, J15
3. Micro USB2 B receptacle connector, J9
4. MicroSD Card socket, J11
5. USB C connector, J10
6. LED light pipes J14 integrating LEDs D1 ... D4
7. 4bit DIP-switch, S2
8. 4bit DIP-switch, S1
9. FTDI FT2232 USB2 to FIFO bridge, U4
10. 3-pin header, J8
11. MAX10 FPGA JTAG/UART 10-pin header, J13
12. Altera MAX10 System Controller FPGA, U18
13. 4-Wire PWM fan connector, J17
14. Zynq MPSoC PL I/O 26-pin header, J16
15. DDR4 SO-DIMM 260-pin socket, U3
16. Battery Holder CR1220, B1
17. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
18. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
19. DC-DC Converter LT8471IFE @+5VA/-5VA, U74
20. DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
21. DC-DC Converter 171050601 @5V, U50
22. Xilinx Zynq Ultrascale+ MPSoC, U1
23. Si5345A 10-output I²C programmable PLL clock, U14
24. Main power fuse @2.5A/16V, F1
25. cPCI slot, J1
26. cPCI slot, J4
27. cPCI slot, J5
28. cPCI slot, J6
29. FTDI FT601Q USB3 to FIFO bridge, U9
30. TI THS5641 8bit DAC ,U28
31. TI THS5641 8bit DAC ,U31
32. TI THS5641 8bit DAC ,U29
33. TI THS5641 8bit DAC ,U33
34. Marvell Alaska 88E1512 GbE PHY ,U20
    

Initial Delivery State

Control Signals

Signals, Interfaces and Pins

Subsections...

USB-C

Front panel USB-C Interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

See FT600Q-FT601Q IC Datasheet for interface details.

MicroUSB

Front panel Micro-USB Interface provides access to UART and JTAG functions via FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.

SD

There are some limitations to use SD card Interface in Linux.

• Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using 1.8V to 3.3V level shifter U10. 
• Micro SD card socket has no "Write Protect" switch.

RJ45 - Ethernet

cPCIe

...

MGT

The TEC0850 board has 30 MGT lines routed to backplane connectors.

MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.

USB Interface

Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.

DDR4 SODIMM Socket

The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.

Circular Push Pull Connector

PicoBlade Connector

Pin Heater 2,54mm (2x5)

Battery holder

On-board Peripherals

Subsections...

Zynq UltraScale XCZU15EG MPSoC

The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.

Main IO interfaces are shown on the image below.

PS MIO Configuration

MAX10 System Controller

System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.

Programmable Clock Generators

I2C

The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.

Oscillators

FTDIs

FT2232H

FT601Q-B-T

Quad-SPI Flash Memory

Board has two N25Q512A11G1240E connected in a dual parallel mode.

EEPROMs

I2C

The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.

USB PHY

Gigabit Ethernet PHY

Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.

8Bit DACs

Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate. 

DIP-Switches

S1

See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are

S2

Buttons

LEDs

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power supply with minimum current capability of 6.65A for system startup is recommended.

The TEC0850 board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
• Programmable Logic (PL)

Power Distribution Dependencies

There are following dependencies how the initial 24V voltage from the main power pins on cPCI slot J1 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Power-On Sequence

The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller FPGA U18:

1. Low-Power Domain (LPD)
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-board voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information.

Voltage Monitor Circuit

The voltages PS_1V8 and VCCINT_0V85 are monitored by the voltage monitor circuit U69, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the low active MR-pin connected to MAX10 FPGA U18 (bank5, pin K10) to GND.

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

1) Temperature range may vary depending on assembly options

2) The operating temperature range of the Zynq MPSoC, SC FPGA SoC and on-board peripherals are junction and also ambient operating temperature ranges

Physical Dimensions

Variants Currently In Production

Revision History

Hardware Revision History

Document Change History

Date Revision Contributor Description change list -- all --

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