<!-- Template Revision 1.3 Basic Notes - export PDF to download, if vivado revision is changed! - Template is for different design and SDSoC and examples, remove unused or wrong description! --> |
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
Zynq PS Design with Linux Example.
<!-- General Design description --> |
<!-- Add Basic Key Features of the design (should be tested) --> |
|
<!-- - Add changes from design - Export PDF to download, if vivado revision is changed! --> |
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2018-09-11 | 2017.4 | te0723-test_board-vivado_2017.4-build_11_20180911144828.zip te0723-test_board_noprebuilt-vivado_2017.4-build_11_20180911144844.zip | John Hartfiel |
|
2018-02-20 | 2017.4 | te0723-test_board-vivado_2017.4-build_06_20180220121024.zip te0723-test_board_noprebuilt-vivado_2017.4-build_06_20180220121039.zip | John Hartfiel |
|
<!-- - add known Design issues and general Notes for the current revision --> |
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
<!-- Add needed external Software --> |
Software | Version | Note |
---|---|---|
Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
<!-- Hardware Support --> |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
te0723-01 | 01 | REV01 | 128MB LPDDR2 | 16MB | ||
te0723-03(r) | r | REV02, REV03 | 128MB DDR3L | 16MB | ||
te0723-03m | m | REV02, REV03 | 512MB DDR3L | 16MB | ||
te0723-03-07s-1c | 7s | REV03 | 512MB DDR3L | 16MB |
Design supports following carriers:
Carrier Model | Notes |
---|---|
--- |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable | Connect to USB2 or better USB3 Hub for proper power supply over USB |
<!-- Remove unused content --> |
For general structure and of the reference design, see Project Delivery
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
---|---|---|
<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
<!-- Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit --> |
Reference Design is available on:
<!-- Basic Design Steps Add/ Remove project specific --> |
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
<!-- Description of Block Design, Constrains... BD Pictures from Export... --> |
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)
Not used on this Example.
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
<!-- Description of Block Design, Constrains... BD Pictures from Export... --> |
Type | Note |
---|---|
DDR | --- |
QSPI | MIO |
USB0 | MIO |
SD1 | MIO |
UART0 | EMIO |
UART1 | MIO |
I2C0 | EMIO |
GPIO | MIO |
USB RST | MIO |
TTC0..1 | MIO |
WDT | MIO |
# # Common bitgen related settings # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] #set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
# # Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design] |
# ####################### # UART0 to FTDI set_property PACKAGE_PIN H14 [get_ports UART_0_txd] set_property PACKAGE_PIN H13 [get_ports UART_0_rxd] set_property PACKAGE_PIN J15 [get_ports UART_0_ctsn] set_property PACKAGE_PIN J14 [get_ports UART_0_rtsn] set_property PACKAGE_PIN K15 [get_ports UART_0_dsrn] set_property PACKAGE_PIN L15 [get_ports UART_0_dtrn] #NC: UART_0_dcdn, UART_0_ri set_property PACKAGE_PIN L14 [get_ports UART_0_dcdn] set_property PACKAGE_PIN M15 [get_ports UART_0_ri] set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*] # ####################### #I2C to J1 connector set_property PACKAGE_PIN P13 [get_ports IIC_0_scl_io] set_property PACKAGE_PIN R13 [get_ports IIC_0_sda_io] set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_scl_io] set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_sda_io] # ####################### #LED to D6 green set_property PACKAGE_PIN G14 [get_ports {USR_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {USR_LED[0]}] # ####################### #USB set_property PACKAGE_PIN F15 [get_ports {USB_OC[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {USB_OC[0]}] set_property PACKAGE_PIN L13 [get_ports {HOST_MODE_EN[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {HOST_MODE_EN[0]}] |
<!-- optional chapter separate sections for different apps --> |
For SDK project creation, follow instructions from:
Xilinx default FSBL
TE modified 2017.4 FSBL
Changes:
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Hello World App in endless loop.
<!-- optional chapter Add "No changes." or "Activate: and add List" --> |
For PetaLinux installation and project creation, follow instructions from:
No changes.
For 128MB variant only:
/include/ "system-conf.dtsi" / { }; /* USB */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; |
No changes.
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
<!-- Add Description for other Software, for example SI CLK Builder ... --> |
No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
<!-- Generate new entry: 1:add new row below first 2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview 3.Update Metadate =Page Information Macro Preview+1 --> |
Date | Document Revision | Authors | Description |
---|---|---|---|
| |||
v.4 | John Hartfiel |
| |
2018-02-20 | v.1 |
| |
All |