Template Revision 2.0 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note:
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Table of contents |
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ZynqMP PS Design with Linux example, simple frequency counter to some CLKs, MGT Aurora Test IP and USB 3 FTDI FIFO IP.
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Not used on this Example.
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GTH Transceiver with Aurora IP:
LED
FMeter
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
create_clock -period 12.800 -name GT_CLK1 [get_nets zusys_i/GT_system/aurora_m_left_0/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] create_clock -period 12.800 -name GT_CLK2 [get_nets zusys_i/GT_system/aurora_m_right_0/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] create_clock -period 12.800 -name GT_CLK3 [get_nets zusys_i/GT_system/aurora_s_left_1/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] create_clock -period 12.800 -name GT_CLK4 [get_nets zusys_i/GT_system/aurora_s_left_2/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] create_clock -period 12.800 -name GT_CLK5 [get_nets zusys_i/GT_system/aurora_s_right_1/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] create_clock -period 12.800 -name GT_CLK6 [get_nets zusys_i/GT_system/aurora_s_right_2/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out] # Test set_property PACKAGE_PIN W7 [get_ports {TEST_CLK_clk_p[0]}] set_property PACKAGE_PIN W6 [get_ports {TEST_CLK_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports TEST_CLK_clk_*] # Bank 44 HD 3.3V set_property PACKAGE_PIN AF15 [get_ports {LED_FP[0]}] set_property PACKAGE_PIN AG15 [get_ports {LED_FP[1]}] set_property PACKAGE_PIN AE15 [get_ports {LED_FP[2]}] set_property IOSTANDARD LVCMOS33 [get_ports LED_FP*] # Bank 50 HD 3.3V #set_property PACKAGE_PIN H11 [get_ports {DAC1_CLK}] #set_property PACKAGE_PIN F10 [get_ports {DAC1_MODE[0]}] #set_property PACKAGE_PIN D11 [get_ports {DAC1_D[0]}] #set_property PACKAGE_PIN D10 [get_ports {DAC1_D[1]}] #set_property PACKAGE_PIN G11 [get_ports {DAC1_D[2]}] #set_property PACKAGE_PIN J11 [get_ports {DAC1_D[3]}] #set_property PACKAGE_PIN G10 [get_ports {DAC1_D[4]}] #set_property PACKAGE_PIN H10 [get_ports {DAC1_D[5]}] #set_property PACKAGE_PIN J10 [get_ports {DAC1_D[6]}] #set_property PACKAGE_PIN E10 [get_ports {DAC1_D[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports DAC1_*] #set_property PACKAGE_PIN F12 [get_ports {DAC2_CLK}] #set_property PACKAGE_PIN F11 [get_ports {DAC2_MODE[0]}] #set_property PACKAGE_PIN G15 [get_ports {DAC2_D[0]}] #set_property PACKAGE_PIN H14 [get_ports {DAC2_D[1]}] #set_property PACKAGE_PIN J14 [get_ports {DAC2_D[2]}] #set_property PACKAGE_PIN G14 [get_ports {DAC2_D[3]}] #set_property PACKAGE_PIN G13 [get_ports {DAC2_D[4]}] #set_property PACKAGE_PIN H13 [get_ports {DAC2_D[5]}] #set_property PACKAGE_PIN H12 [get_ports {DAC2_D[6]}] #set_property PACKAGE_PIN J12 [get_ports {DAC2_D[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports DAC2_*] # Bank 44 HD 3.3V #set_property PACKAGE_PIN AK15 [get_ports {DAC3_CLK}] #set_property PACKAGE_PIN AK14 [get_ports {DAC3_MODE[0]}] #set_property PACKAGE_PIN AG14 [get_ports {DAC3_D[0]}] #set_property PACKAGE_PIN AE13 [get_ports {DAC3_D[1]}] #set_property PACKAGE_PIN AG13 [get_ports {DAC3_D[2]}] #set_property PACKAGE_PIN AJ15 [get_ports {DAC3_D[3]}] #set_property PACKAGE_PIN AJ14 [get_ports {DAC3_D[4]}] #set_property PACKAGE_PIN AH14 [get_ports {DAC3_D[5]}] #set_property PACKAGE_PIN AF13 [get_ports {DAC3_D[6]}] #set_property PACKAGE_PIN AH13 [get_ports {DAC3_D[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports DAC3_*] #set_property PACKAGE_PIN AL12 [get_ports {DAC4_CLK}] #set_property PACKAGE_PIN AK13 [get_ports {DAC4_MODE[0]}] #set_property PACKAGE_PIN AP14 [get_ports {DAC4_D[0]}] #set_property PACKAGE_PIN AN14 [get_ports {DAC4_D[1]}] #set_property PACKAGE_PIN AM14 [get_ports {DAC4_D[2]}] #set_property PACKAGE_PIN AN13 [get_ports {DAC4_D[3]}] #set_property PACKAGE_PIN AP12 [get_ports {DAC4_D[4]}] #set_property PACKAGE_PIN AN12 [get_ports {DAC4_D[5]}] #set_property PACKAGE_PIN AL13 [get_ports {DAC4_D[6]}] #set_property PACKAGE_PIN AM13 [get_ports {DAC4_D[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports DAC4_*] # Bank 64 HP 1.8V set_property PACKAGE_PIN AL6 [get_ports FIFO_CLK] set_property IOSTANDARD LVCMOS18 [get_ports FIFO_CLK] set_property PACKAGE_PIN AM8 [get_ports {FTDI_RESET_N}] set_property IOSTANDARD LVCMOS18 [get_ports {FTDI_RESET_N}] set_property PACKAGE_PIN AN8 [get_ports {WAKEUP_N}] set_property IOSTANDARD LVCMOS18 [get_ports {WAKEUP_N}] set_property PACKAGE_PIN AJ12 [get_ports {RXF_N}] set_property IOSTANDARD LVCMOS18 [get_ports {RXF_N}] set_property PACKAGE_PIN AK12 [get_ports {TXE_N}] set_property IOSTANDARD LVCMOS18 [get_ports {TXE_N}] set_property PACKAGE_PIN AM10 [get_ports {BE[0]}] set_property PACKAGE_PIN AK10 [get_ports {BE[1]}] set_property PACKAGE_PIN AM11 [get_ports {BE[2]}] set_property PACKAGE_PIN AL11 [get_ports {BE[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {BE[*]}] set_property PACKAGE_PIN AL10 [get_ports {SIWU_N}] set_property IOSTANDARD LVCMOS18 [get_ports {SIWU_N}] set_property PACKAGE_PIN AM9 [get_ports {WR_N}] set_property IOSTANDARD LVCMOS18 [get_ports {WR_N}] set_property PACKAGE_PIN AK9 [get_ports {RD_N}] set_property IOSTANDARD LVCMOS18 [get_ports {RD_N}] set_property PACKAGE_PIN AL8 [get_ports {OE_N}] set_property IOSTANDARD LVCMOS18 [get_ports {OE_N}] set_property PACKAGE_PIN AK1 [get_ports {DATA[0]}] set_property PACKAGE_PIN AJ10 [get_ports {DATA[1]}] set_property PACKAGE_PIN AJ9 [get_ports {DATA[2]}] set_property PACKAGE_PIN AK7 [get_ports {DATA[3]}] set_property PACKAGE_PIN AK5 [get_ports {DATA[4]}] set_property PACKAGE_PIN AM1 [get_ports {DATA[5]}] set_property PACKAGE_PIN AL2 [get_ports {DATA[6]}] set_property PACKAGE_PIN AK4 [get_ports {DATA[7]}] set_property PACKAGE_PIN AN1 [get_ports {DATA[8]}] set_property PACKAGE_PIN AL3 [get_ports {DATA[9]}] set_property PACKAGE_PIN AK8 [get_ports {DATA[10]}] set_property PACKAGE_PIN AN2 [get_ports {DATA[11]}] set_property PACKAGE_PIN AP2 [get_ports {DATA[12]}] set_property PACKAGE_PIN AL7 [get_ports {DATA[13]}] set_property PACKAGE_PIN AL5 [get_ports {DATA[14]}] set_property PACKAGE_PIN AM4 [get_ports {DATA[15]}] set_property PACKAGE_PIN AN4 [get_ports {DATA[16]}] set_property PACKAGE_PIN AM5 [get_ports {DATA[17]}] set_property PACKAGE_PIN AM6 [get_ports {DATA[18]}] set_property PACKAGE_PIN AN3 [get_ports {DATA[19]}] set_property PACKAGE_PIN AP3 [get_ports {DATA[20]}] set_property PACKAGE_PIN AP4 [get_ports {DATA[21]}] set_property PACKAGE_PIN AP5 [get_ports {DATA[22]}] set_property PACKAGE_PIN AN6 [get_ports {DATA[23]}] set_property PACKAGE_PIN AN7 [get_ports {DATA[24]}] set_property PACKAGE_PIN AP6 [get_ports {DATA[25]}] set_property PACKAGE_PIN AP7 [get_ports {DATA[26]}] set_property PACKAGE_PIN AP11 [get_ports {DATA[27]}] set_property PACKAGE_PIN AP10 [get_ports {DATA[28]}] set_property PACKAGE_PIN AP9 [get_ports {DATA[29]}] set_property PACKAGE_PIN AN9 [get_ports {DATA[30]}] set_property PACKAGE_PIN AP8 [get_ports {DATA[31]}] set_property IOSTANDARD LVCMOS18 [get_ports {DATA[*]}] # Bank 66 HP 1.8V set_property PACKAGE_PIN Y8 [get_ports {CLK2_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {CLK2_clk_p[0]}] create_clock -period 8.000 -name CLK2 [get_ports {CLK2_clk_p[0]}] # MGT set_property PACKAGE_PIN L27 [get_ports {CLK4_clk_p}] set_property PACKAGE_PIN G8 [get_ports {CLK1_clk_p} |
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For SDK project creation, follow instructions from:
Template location: ./sw_lib/sw_apps/
TE modified 2018.2 FSBL
Changes:
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
TE modified 2018.2 FSBL
Changes:
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
Xilinx default PMU firmware.
Hello TEC0850 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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For PetaLinux installation and project creation, follow instructions from:
No changes.
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ "set dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */ #ifdef CONFIG_ZYNQMP_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_CMD_EEPROM #define CONFIG_ZYNQ_EEPROM_BUS 5 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 #endif |
/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* USB 2.0 */ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; }; &dwc3_1 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; }; /* SD*/ &sdhci1 { disable-wp; no-1-8-v; }; /* SPI */ // &spi0 { // num-cs = <1>; // ext_command:spidev@0{ // compatible="spidev"; // reg = <0>; //chipselect 0 // spi-max-frequency= <100000>; // spidev-name = "EXT"; // }; // }; // /* I2C */ // &i2c0 { // #address-cells = <1>; // #size-cells = <0>; // }; &i2c1{ // TEC0850 #address-cells = <1>; #size-cells = <0>; // Instantiate EEPROM driver eeprom153: eeprom@53 { compatible = "atmel,24c02"; reg = <0x53>; }; // Instantiate EEPROM driver eeprom150: eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; }; // There is also Clock generator chip // Si5345 at address 0x69, but there is // no standard driver in Linux kernel yet }; |
Deactivate:
CONFIG_CPU_IDLE (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ (only needed to fix JTAG Debug issue)
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
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No additional software is needed.
File location <design name>/misc/Si5345/RegisterMap.txt
General documentation how you work with these project will be available on Si5345
To get content of older revision got to "Change History" of this page and select older document revision number.
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