Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template (note: inner scroll ignore/only only with drawIO object):
Create DrawIO object here: Attention if you copy from other page, use
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux
<design name>/os/petalinux
PetaLinux template with current configuration
Additional Sources
Type
Location
Notes
init.sh
<design name>/sd/
Additional Initialization Script for Linux
Prebuilt
Notes :
prebuilt files
Template Table:
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.hdf
Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Important set new Vivado version link on every Design update of new vivado version!
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
(optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (uboot.elf and image.ub) with exported HDF
HDF is exported to "prebuilt\hardware\<short name>" Note: HW Export from Vivado GUI create another path as default workspace.
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup optional "TE::pr_program_flash_binfile -swapp hello_te0720" possible
Copy image.ub on SD-Card
Insert SD-Card
SD
Copy image.ub and Boot.bin on SD-Card.
For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Select SD Card as Boot Mode (or QSPI - depending on step 1) Note: See TRM of the Carrier, which is used.
Power On PCB Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
Open Serial Console (e.g. putty)
Speed: 115200
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console: Note: Wait until Linux boot finished For Linux Login use:
User Name: root
Password: root
You can use Linux shell now.
I2C 0 Bus type: i2cdetect -y -r 0
I2C 1 Bus type: i2cdetect -y -r 1
RTC check: dmesg | grep rtc
ETH0 works with udhcpc
USB: insert USB device
Option Features
Webserver to get access to Zynq
insert IP on web browser to start web interface
init.sh scripts
add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
Vivado HW Manager
Note:
Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
add controllable IOs with short notes..
Monitoring:
add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder
Monitoring: PHY LED
System Design - Vivado
Note:
Description of Block Design, Constrains... BD Pictures from Export...
Block Design
PS Interfaces
Note:
optional for Zynq / ZynqMP only
add basic PS configuration
Type
Note
DDR
---
QSPI
MIO
ETH0
MIO
USB0
MIO
SD0
MIO
SD1
MIO
UART0
MIO
UART1
MIO
I2C0
MIO
I2C1
EMIO
GPIO
MIO
TTC0..1
EMIO
WDT
EMIO
Constrains
Basic module constrains
#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design
To get content of older revision got to "Change History" of this page and select older document revision number.
Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports