some sources available on public doc TEBT0808 TRM
Template Revision 2.5
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TEBT0808-01 is a testboard for module TE0808 (REV 02 and 03) as well as for TE0803 (REV 01).
Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.
Key Features
- Accepts TE0808 / TE0803
- Single 3.3V input
- Header for TE0790 JTAG/UART Adapter
- 20 Pin ARM JTAG header (connected to MIO JTAG 0)
- 10 Pin I2C header for Silabs Clock Builder Field Programmer
- Done, Error/Status LEDs
- One PL GT with SMA connectors
- One PS GT with SMA connectors
- GT local loopback
- PL I/O loopbacks
- PS I/O loopbacks
- Boot Mode switches
- Power control switches to control TE0808 power domains
- One pre-assembled TE0790 XMOD FTDI JTAG adapter
Supported Bootmodes are SPI and JTAG.
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Uninsulated 2 mm rigid socket. J8-J7
- SMA Coaxial straight. J6- J9...15
- Surface Mount Schottky Barrier Rectifier. D1
- Box Headers, Straight/Angled J5-J16
- Board to Board Connector. J1...4
- Clock Oscillator, U2
- On-Board LED, D2...4
- DIP-Switch, S1...3
- XMOD JTAG Base,
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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- | - | - |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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Boot mode can be set by DIP-Switch S1.
M3 | M2 | M1 | M0 | Bootmode Hex | Bootmode | Notes |
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ON | ON | ON | ON | 0x0 | PS Main JTAG (TE0790 USB JTAG) | Needed for SPI Flash Programming | ON | ON | OFF | ON | 0x2 | SPI Flash (dual parallel, 4bit x 2, 32bit Addressing) | Default |
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Signal | B2B | Note |
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PLL_RST | J2-89 |
| SRST_B | J2-96 | connected to PJTAG0_SRST - J16 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
B2B Connector | Interfaces | Number of I/O | Notes |
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J1
| User I/O | 22 singel ended, 11 Differential 8 singel ended, 4 Differential 8 singel ended, 4 Differential 8 singel ended, 4 Differential 3 singel ended | Connected to Bank 66 Connected to Bank 228 Connected to Bank 229 Connected to Bank 230 VCCO_66, PL_1V8 | J2
| Ethernet PHY | 32 singel ended, 16 Differential 4 singel ended, 16 Differential | Connected to Bank 505 Connected to Bank 128 | Control Signals | 15 single ended | PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE | Power Control Signal | 10 single ended | EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L | JTAG Interface | 7 single ended | TCK, TDI, TMS, TDO, MR, Rxd, Txd | WANNE2 | 2 single ended | PLL_SCL, PLL_SDA | Clock | 6 singel ended, 3 Differential | CLK0, CLK7, CLK8 | J3
| User I/O | 12 singel ended, 6 Differential 12 singel ended, 6 Differential | Connected to Bank 48 Connected to Bank 47 | Clock | 6 singel ended, 3 Differential | CLK228, CLK229, CLK230 | PJTAG Interface | 7 single ended | PJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO, | MIO | 27 single ended | MIO19..76 | UART | 2 single ended | TXD, RXD | Power pins | 4 single ended | PS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47 | J4 | User I/O | 48 singel ended, 62 Differential 4 single ended | Connected to Bank 64 Connected to Bank 64 | Power pins | 4 single ended | VCCO_64, VCCO65 |
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JTAG Interface
JTAG access to the TE0803 or TE0808 SoM through B2B connector JM2.
JTAG Signal | B2B Connector |
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TMS | J2-126 | TDI | J2-122 | TDO | J2-124 | TCK | J2-120 | MR | J2-83 | RXD | J3-141 | TXD | J3-139 |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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Oscillator | U2 | 125.00 MHz |
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DIP Switch
There are thre DIP Switches, S1, S2, S3.
The Boot Mode can be set through DIP Switch S1, refer to BootMode table.
Signals | B2B | S1 switch | Notes |
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MODE0 | J2-109 | S1A |
| MODE1 | J2-107 | S1B |
| MODE2 | J2-105 | S1C |
| MODE3 | J2-103 | S1D |
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Control signals must be set by DIP Switch S2, S3.
Signals | B2B | S2 switch | Notes |
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EN_PSGT | J2-84 | S2A |
| EN_GT_R | J2-95 | S2B |
| EN_GT_L | J2-97 | S2C |
| EN_PLL_PWR | J2-77 | S2D | connected to PG_PL |
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Signals | B2B | S3 switch | Notes |
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EN_DDR | J2-112 | S3A |
| EN_LPD | J2-108 | S3B |
| EN_PL | J2-101 | S3C |
| EN_FPD | J2-102 | S3D |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D2 | Red | DONE | Low |
| D3 | Red | ERR_STATUS | Low |
| D4 | Red | ERR_OUT | Low |
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Clock Sources
Designator | Description | Frequency | Note |
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U2 | MEMS Oscillator | 125.00 MHz |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
TestKits are pre-assembled and pre-flashed with initial Flash image, they start up as soon as power (3.3V) is applied.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
If you connect the power supply with wrong polarity, Diod D1 protects the board not to be damaged.
Power Rails
Power Rail Name | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | B2B JM4 Pin | Direction | Notes |
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VCCO_66 | 90,120 | - | - | - | Output | Connected to 1.8 (PL_1V8) | 3.3V | - | 138...160 | - | - | Input |
| PS_BATT | - | 125 | - | - | Output | Connected to 1.8 (PS_1V8) | VCCO_47 | - | - | 43, 44 | - | Output | Connected to SI_PLL_1V8 | VCCO_48 | - | - | 15,16 | - | Output | Connected to SI_PLL_1V8 | PS_1V8 | - | - | 147, 148 | - | Output |
| PLL_3V3 | - | - | 152 | - | Output | 3.3V | VCCO_64 | - | - | - | 58,106 | Output | Connected to 1.8 (PL_1V8) | VCCO_65 | - | - | - | 69,105 | Output | Connected to 1.8 (PL_1V8) |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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TEBT0808 has four Razor Beam™ LP Slim Terminal Strip.
Technical Specifications
Absolute Maximum Ratings
Symbols | Min | Max | Unit | Note |
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VIN | 0 | 3.3 | V | Input Supply Voltage | Storage Temperatur | -40 | +85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Symbols | Min | Max | Unit | Note |
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VIN | 0 | 3.3 | V | Input Supply Voltage | Storage Temperatur | -40 | +85 | °C |
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Physical Dimensions
PCB thickness: 1.6 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Document Change History
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Disclaimer