Template Revision 2.6
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Table of Contents |
Overview
The Trenz Electronic TEI0015 is an commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
Key Features
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- SMA Connector, J5...6
- Instrumentation Amplifier, U12- U14
- Series Voltage Reference, U8
- Analog to Digital Convertor, U15- U6
- Voltage Regulator, U10- U13- U16
- Buck Switching Regulator, U11- U4
- Intel® MAX 10, U1
- SDRAM Memory, U2
- SPI Flash Memory, U5
- USP to UART convertor, U3
- User LEDs, D2...9
- 4Kb EEPROM, U9
- Switch, S1...2
- USB port, J9
- Pin Holder (Not assembled), J1...4
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| I2C Configuration EEPROM | Programmed |
| SDRAM | Not Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
Signal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | connected to nCONFIG |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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Bank 1A | J1 | 7 | 3.3V | AIN0...6 | Bank 1B | J4 | 5 | 3.3V | JTAG interface | Bank 2 | J1 | 4 | 3.3V | DIO2...5 | Bank 5 | J2 | 9 | 3.3V | DIO6...14 | J1 | 2 | 3.3V | DIO0...1 | Bank 8 | J2 | 1 | 3.3V | RESET |
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FPGA I/O Banks
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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FPGA Bank | I/O Signal Count | Connected to | Notes |
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Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | 1 | Jumper, J3 | AIN7 | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2 | 4 | 1x14 Pin header, J1 | D2...5 |
| 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV |
| 1 | 12MHz Oscillator, U7 | CLK12M |
| 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | 2 | 1x14 Pin header, J1 | DIO0...1 | 1 | D12_R | DIO12 | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | 2 | SDRAM, U2 | DQM0...1 | 1 | D11_R | DIO11 | Bank 8 | 8 | User Red LEDs, D2...9 | LED0...7 |
| 6 | SPI Flash, U5 | F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn |
| 1 | Red LED, D10 | CONF_DONE |
| 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 |
| 1 | Push Button, S2 | USER_BTN |
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JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
JTAG Signal | Pin Header Connector | Note |
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TMS | J4-6 |
| TDI | J4-5 |
| TDO | J4-4 |
| TCK | J4-3 |
| JTAG_EN | J4-2 |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
SDRAM
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | Data input/output | DQ0 ... DQ15 | bank 6 | - | Data mask | DQM0 ... DQM1 | bank 6 | - | Clock | CLK | bank 3 |
| Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | ADBUS1 | TDI | FPGA bank 1B, pin F5 | ADBUS2 | TDO | FPGA bank 1B, pin F6 | ADBUS3 | TMS | FPGA bank 1B, pin G1 | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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SPI Flash Memory
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
Signal Schematic Name | Connected to | Notes |
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F_CS | FPGA bank 8, pin B3 | chip select | F_CLK | FPGA bank 8, pin A3 | clock | F_DI | FPGA bank 8, pin A2 | data in / out | nSTATUS | FPGA bank 8, pin C4 | data in / out, configuration dual-purpose pin of FPGA | DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA | F_DO | FPGA bank 8, pin B2 | data in / out |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
Schematic | Connected to | Notes |
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EECS | FTDI U3, Pin EECS |
| EECLK | FTDI U3, Pin EECLK |
| EEDATA | FTDI U3, Pin EEDATA |
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A2D Convertor
The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).
Pins | Connected to | Notes |
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IN+ | Diff Amplifier U14, VOUT- |
| IN- | Diff Amplifier U14, VOUT+ |
| SDI | Bank 2, ADC_SDI |
| SDO | Bank 2, ADC_SDO |
| SCK | Bank 2, ADC_SCK |
| CNV | Bank 2, ADC_CNV |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D2...9 | Red | LED1...8 | Active High | User LEDs | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on |
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Micro-USB2 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
Pins | Connected to | Note |
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VBUS | USB_VBUS | It is connected to GND | D+ | FTDI U3, DP pin |
| D- | FTDI U3, DM pin |
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Clock Sources
Clock Source | Schematic Name | Frequency | Note |
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Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
To power-up the module, power supply with minimum current capability of 1A is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage Monitor Circuit
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Power Rails
Connector Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Notes |
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J2
| VIN | 5V | Input |
| 3.3V | 3.3V | Output |
| 5V | 5V | Output |
| J9 | USB_VBUS | 5V | Input |
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Bank Voltages
| Schematic Name | | Notes |
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Bank 1A | VCCIO1A | 3.3V |
| Bank 1B | VCCIO1B | 3.3V |
| Bank 2 | VCCIO2 | 3.3V |
| Bank 3 | VCCIO3 | 3.3V |
| Bank 5 | VCCIO5 | 3.3V |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 8 | VCCIO8 | 3.3V |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: ?? mm.
Currently Offered Variants
Revision History
Hardware Revision History
List of online PCN ...Link
Document Change History
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Date | Revision | Contributor | Description |
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Disclaimer