Template Revision 2.1 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
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Table of contents |
Overview
Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.
Key Features
Notes : - Add basic key futures, which can be tested with the design
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- PetaLinux
- SD
- ETH
- USB
- I2C
- RTC
- FMeter
- SI5338 Initialisation with FSBL (optional)
- Special FSBL for QSPI Programming
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Revision History
Notes : - add every update file on the download
- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2018-10-01 | 2018.2 | TE0715-test_board-vivado_2018.2-build_03_20181001131411.zip TE0715-test_board_noprebuilt-vivado_2018.2-build_03_20181001131421.zip | John Hartfiel | - Rework Board Part Files (PS)
- small design changes
- SI5338 reconfiguration default activated on FSBL
- update linux startup app
| 2018-04-26 | 2017.4 | TE0715-test_board-vivado_2017.4-build_07_20180426171530.zip TE0715-test_board_noprebuilt-vivado_2017.4-build_07_20180426171546.zip | John Hartfiel | | 2018-03-27 | 2017.4 | te0715-test_board-vivado_2017.4-build_07_20180327223552.zip te0715-test_board_noprebuilt-vivado_2017.4-build_07_20180327223606.zip | John Hartfiel | - Board Part Bug fix with UART 1
| 2018-01-05 | 2017.4 | te0715-test_board-vivado_2017.4-build_01_20180105195436.zip te0715-test_board_noprebuilt-vivado_2017.4-build_01_20180105195452.zip | John Hartfiel | - No Design changes
- Add FSBL for Flash Programming
| 2017-11-10 | 2017.2 | te0715-test_board-vivado_2017.2-build_05_20171110134232.zip te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip | John Hartfiel | - New Web Link on Board Part Files
- Add optional FSBL Code to reprogram SI5338
| 2017-10-19 | 2017.2 | te0715-test_board-vivado_2017.2-build_04_20171019141808.zip te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip | John Hartfiel | - changed Flash typ on TE0715_board_files.csv
(older one is not supported on Vivado 2017.2)
| 2017-09-22 | 2017.2 | te0715-test_board-vivado_2017.2-build_02_20170927143412.zip te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip | John Hartfiel | |
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Release Notes and Know Issues
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround | To be fixed version |
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Timing problems with Frequency counter | can be ignored | --- | with 2018-10-01 update |
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Requirements
Software
Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vivado | 2018.2 | needed | SDK | 2018.2 | needed | PetaLinux | 2018.2 | needed | SI5338 Clock Builder | --- | optional |
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Hardware
Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TE0715-03-15-1C | 03_15_1c | REV01,02,03 | 1GB | 32 |
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| TE0715-03-15-1I | 03_15_1i | REV01,02,03 | 1GB | 32 |
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| TE0715-03-15-2I | 03_15_2i | REV01,02,03 | 1GB | 32 |
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| TE0715-03-30-1C | 03_30_1c | REV01,02,03 | 1GB | 32 |
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| TE0715-03-30-1I | 03_30_1i | REV01,02,03 | 1GB | 32 |
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| TE0715-03-30-3E | 03_30_3e | REV01,02,03 | 1GB | 32 |
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| TE0715-04-15-1C | 04_15_1c | REV04 | 1GB_L | 32 |
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| TE0715-04-15-1I | 04_15_1i | REV04 | 1GB_L | 32 |
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| TE0715-04-15-1I3 | 04_15_1i | REV04 | 1GB_L | 32 |
| 2,5 mm B2B connector | TE0715-04-15-2I | 04_15_2i | REV04 | 1GB_L | 32 |
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| TE0715-04-30-1C | 04_30_1c | REV04 | 1GB_L | 32 |
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| TE0715-04-30-1I | 04_30_1i | REV04 | 1GB_L | 32 |
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| TE0715-04-30-1I3 | 04_30_1i | REV04 | 1GB_L | 32 |
| 2,5 mm B2B connector | TE0715-04-30-3E | 04_30_3e | REV04 | 1GB_L | 32 |
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| TE0715-04-12s-1C | 12s | REV04 | 1GB_L | 32 |
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| TE0715-04-30-1IA | 04_30_1i | REV04 | 1GB_L | 32 |
| Micron instead of Spansion Flash |
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Design supports following carriers:
Carrier Model | Notes |
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TE0701 |
| TE0703 | used as reference carrier | TE0705 |
| TE0706 |
| TEBA0841 |
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Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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Content
For general structure and of the reference design, see Project Delivery
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
Type | Location | Notes |
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SI5338 | <design name>/misc/Si5338 | SI5345 Project with current PLL Configuration |
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Prebuilt
Notes : - prebuilt files
- Template Table:
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Note:- Programming and Startup procedure
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch. TE0715-0x-30-xx only: HP IO Banks max power supply voltage is 1.8V. |
Programming
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0715" possible - Copy image.ub on SD-Card
- Insert SD-Card
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
Vivado HW Manager
CLK Counters:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL, see FSBL description).
System Design - Vivado
Block Design
PS Interfaces
Activated interfaces:
Type | Note |
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DDR | --- | QSPI | MIO | I2C1 | MIO | UART0 | MIO | GPIO | MIO | ETH, USB Rst | MIO | SD0 | MIO | USB0 | MIO | ETH0 | MIO | TTC0..1 | EMIO | WDT | EMIO |
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Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]] |
# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/BUFG_O[0]}] |
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Application
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2018.2 FSBL
Changes:
- Si5338 Configuration
- see main.c, fsbl_hooks.c (d/remove define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup (default activate))
- Add register_map.h, si5338.c, si5338.h
zynq_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0715
Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
<!--
- optional chapter, if petalinux is used
- Add changes from default petalinux project
--> |
For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
No changes.
Device Tree
/include/ "system-conf.dtsi"
/ {
};
/* default */
/* ETH PHY */
&gem0 {
status = "okay";
ethernet_phy0: ethernet-phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
};
};
/* USB PHY */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
//compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50
&i2c1 {
rtc@6F { // Real Time Clock
compatible = "isl12022";
reg = <0x6F>;
};
};
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Kernel
Activate:
Rootfs
Activate:
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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SI5338
File location <design name>/misc/Si5338/RegisterMap.txt
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | Authors | Description |
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| | - Release 2018.2
- Redesign Board Part Files
- New activate SI5338 example over FSBL
- small Design changes
- Update Documentation Style
| - Release 2018.2
- Redesign Board Part Files
- New activate SI5338 example over FSBL
- small Design changes
- Update Documentation Style
- Update in process and will be available soon
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| | v.30 | John Hartfiel | | | v.29 | John Hartfiel | | 2018-02-13 | v.28 | John Hartfiel | | 2017-11-10 | v.22 | John Hartfiel | - Design Update with new options
- Add Si5338 section
- Update FSBL section
| 2017-10-19 | v.21 | John Hartfiel | | 2017-10-19 | v.20 | John Hartfiel | | 2017-10-06 | v.18 | John Hartfiel | - Text correction
- Update Launch section
- Supported PCBs
| 2017-10-02 | v.14 | John Hartfiel | - Document update on Prebuilt section
| 2017-09-28 | v.13 | John Hartfiel | | -- | all | | -- |
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Legal Notices