Template Revision 27

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

he Trenz Electronic TEI0006 is an Industrial grade module based on Intel® Cyclone 10 GX. Intel Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.

Refer to http://trenz.org/tei0006-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .







Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .







  1. Intel® MAX 10, U18
  2. DC/DC convertor, U4...11
  3. SDRAM DDR3 Memory, U12...13
  4. User LEDs, D1...4
  5. Ethernet Tranciever, U2- U14
  6. SPI Flash Memory, U1- U3
  7. Intel® Cyclone 10 GX, U23
  8. EEPROM, U64
  9. Buffer, U16

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMProgrammed


DDR3 SDRAMNot Programmed



Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

The TEI00006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.

MODE Signal State

MSEL2MSEL1MSEL0Boot Mode

MSEL[2:0]

010

AS x4 / Fast

011

AS x1 / Standard

000PS and FPP/ Fast
001PS and FPP/ Standard


By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

SignalsConnected toDescriptionNote
nCONFIG1.8VConfiguration triggerFrom U18( Intel MAX 10) - Bank 3
CONF_DONE1.8VConfiguration done To U18( Intel MAX 10) - Bank 3
nSTATUS1.8VConfiguration status To U18( Intel MAX 10) - Bank 3
DCLKU1,U3Configuration clock 

To U1(Flash Memory)

From U18( Intel MAX 10) - Bank 3

AS_DATA0...3U1Configuration dataTo U1(Flash Memory)



Signal

B2BConnected toNote

PERST

J2-99Bank A2


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGAFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
Intel Cyclone 10 GXBank 1CJ324 Single ended (12 Diff pair)0.95V

Bank 1D

J324 Single ended (12 Diff pair)0.95V
Bank 2AJ21 Single ended1.8VPERST
Bank 2JJ246 Single ended (23 Diff pair)1.8V
Bank 2KJ146 Single ended (23 Diff pair)VCCIO2K
Bank 2LJ146 Single ended (23 Diff pair)3.0V
Bank 3A--1.35VVDD_DDR
Bank 3B--1.35VVDD_DDR
Intel Max 10Bank 1AJ28 Single ended3.3V
Bank 1BJ25 Single ended3.3V
Bank 2J32 Single ended1.8VIO
Bank 3--1.8VIO
Bank 5J24 Single ended3.3V
Bank 6J22 Single ended3.3V
Bank 8J225 Single ended3.3V



JTAG Interface

JTAG access to the TEI0006 SoM through B2B connector JM2.

JTAG Signal

B2B Connector

Note
TMSJ2-160
TDIJ2-159
TDOJ2-158
TCK

J2-157


JTAG_ENJ2-105Connected to 3.3V


MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



MIO PinConnected toB2BNotes
MAX_IO1...22U18( Intel MAX 10) - Bank 8J2
MAX_IO23...26U18( Intel MAX 10) - Bank 8J2



On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes

SPI Flash Memory

U1- U3
EEPROMU64
SDRAM DDR3 MemoryU12...13
Ethernet TrancieverU2- U14
Intel Max 10U18

User LEDs

D1...4D1 (Red), D2...4 (Green)
OscillatorsU14, U15, U17, U21


SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

DesignatorSchematicConnected toNotes
U1



NCSOCSS Bank (Configuration Bank)Used when you are not configuring using AS
DCKDCLKAS Configuration Clock
AS_DATA0CSS Bank (Configuration Bank)AS Configuration Pin
AS_DATA1CSS Bank (Configuration Bank)AS Configuration Data
AS_DATA2CSS Bank (Configuration Bank)AS Configuration Data
AS_DATA3CSS Bank (Configuration Bank)AS Configuration Data
U3QSPI_CSBank 2A
QSPI_CKBank 2A
QSPI_DATA0Bank 2A
QSPI_DATA1Bank 2A
QSPI_DATA2Bank 2A
QSPI_DATA3Bank 2A


EEPROM

SchematicU64 PinB2BNotes
I2C_SCLSCLJ3-135Connected to Bank 2 of Intel Max 10
I2C_SDASDAJ3-137Connected to Bank 2 of Intel Max 10



PinsI2C AddressDesignatorNotes
I2C_SCL, I2C_SDA0x53U64


DDR3 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0006 SoM has two 1 Gb volatile DDR3 SDRAM IC for storing user application code and data.

Ethernet

Signal NameConnected toB2BSignal Description

PHY1_MDI0_P

PHY1_MDI0_N

-

-

J2-93

J2-91


PHY1_MDI1_P

PHY1_MDI1_N

-

-

J2-87

J2-85


PHY1_MDI2_P

PHY1_MDI2_N

-

-

J2-81

J2-79


PHY1_MDI3_P

PHY1_MDI3_N

-

-

J2-75

J2-73


ETH1_RSTBank 2A-Connected to DVDDH Voltage
ETH1_MDCBank 2A-Connected to DVDDH Voltage
ETH1_MDIOBank 2A-Connected to DVDDH Voltage
ETH1_TXD0...7Bank 2A-Transfer
ETH1_RXD0...7Bank 2A-Recieve
ETH1_GTXCKBank 2A-
ETH1_TXCLKBank 2A-
ETH1_TXEN--
ETH1_TXER--
ETH1_RXCKBank 2A-Connected to GNG
ETH1_RXDVBank 2A-Connected to GNG
PHY1_INT--Connected to DVDDH Voltage
PHY1_LED1-

J2-69

Connected to DVDDH Voltage
PHY1_LED2-J2-67Connected to GNG
ETH1_CRSBank 2A-
ETH1_XTAL_INETH_CLKIN-From U21 (25MHz MEMS Oschillator)


Intel MAX 10

The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM. 

Intel Max 10 BankSignalsConnected to DescriptionNotes
Bank 1AAIN0...7B2B- J2

Bank 1BTCK, TDO, TMS, TDI, JTAGENB2B- J2

Bank 2

PHY1_LED1

PHY1_LED2

U23(Ethernet)

U23(Ethernet)

Ethernet LED

Ethernet LED

Tight to GND

Tight to DVDDH

F_TCK, F_TDO, F_TDI, F_TMSU23(Intel Cyclone 10 GX) - Bank CSSIntel Cyclone 10 JTAG signals
I2C_SDA, I2C_SCL

U64(EEPROM)

J3 (B2B)

U14 (Programmable Oscillator)

I2C EEPROM signals
PLL_RST

U14 (Programmable Oscillator)

Oscillator reset signal
Bank 3nSTATUS, nCONFIG, CONF_DONEU23(Intel Cyclone 10 GX) - Bank CSSIntel Cyclone 10 Configuration signals
DCLK

U23(Intel Cyclone 10 GX) - Bank CSS

U1(SPI Flash)

Intel Cyclone 10

Configuration clock from Flash memory


MSEL0...1U23(Intel Cyclone 10 GX) - Bank CSS

Intel Cyclone 10

Configuration mode signals


DEV_CLRN, INIT_DONEU23(Intel Cyclone 10 GX) - Bank 2A

M10_IO0...4U23(Intel Cyclone 10 GX) - Bank 2A

Bank 5

DIS_GROUP1...4T1...4 (N- Channel MOSFET)Fast Discharching
MAX_IO23...26J2 (B2B)Intel MAX 10 GPIO

PG_0.95V, EN_0.95V

PG_1.8VIO, EN_1.8VIO

U7(Voltage Regulator)

U7(Voltage Regulator)

Power control signals
Bank 6




M10_CLKU21(25MHz Oscillator)Intel MAX 10 Clock

VADJ_VS0...2, VADJ_EN

PG_1.35V, EN_1.35V

PG_1.8V, EN_1.8V

PG_VTT, EN_VTT

PG_0V9, EN_0V9

U11(Voltage Regulator)

U8(Voltage Regulator)

U5(Voltage Regulator)

U9(Voltage Regulator)

U4(Voltage Regulator)

Power control signals
PHY1_33LED1...2

J2 (B2B)

Ethernet LED

LED_FP_1

LED_FP_2...4

D1

D2...4

User LEDs

Red LED

Green LED

Bank 8

M10_nSTATUS, M10_nCONFIG, M10_CONF_DONE

J2(B2B)Intel MAX 10 configuration signals
MAX_IO1...22J2(B2B)Intel MAX 10 GPIO



LEDs

DesignatorColorConnected toActive LevelNote
D1RedLED_FP_1Active high
D2GreenLED_FP_2Active high
D3GreenLED_FP_3Active high
D4GreenLED_FP_4Active high


Clock Sources

The TEI0006 has three MEMS oscillator and a programmable clock generator. 

SignalsClock TypeIn/ OutConnected toFrequencyNote

IN1_P

IN1_N

Differential

In

In

U15 (Oscillator)

GND

25 MHz
IN1..3 DifferentialInJ3(B2B)Variable

XA

XB

Differential

U17 (Oscillator)

GND

48 MHz

CLK0...4

DifferentialOutJ3(B2B)25MHz
REFCLK_EMIFPDifferentialOut-Variable
CLK6...7DifferentialOutU23 (Intel Cyclon 10 GX)- Bank 1DVariable
CLK8...9DifferentialOutU23 (Intel Cyclon 10 GX)- Bank 1CVariable



DesignatorDescriptionFrequencyNote
U21MEMS Oscillator25MHz
U15MEMS Oscillator25MHz
U17MEMS Oscillator48MHz
U14Programmable OscillatorVariable


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies





Power-On Sequence




Voltage Monitor Circuit


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power Rails


Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit




V




V




V




V




V




V




V




V











Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



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Physical Dimensions

In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.


Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

DateRevisionChanges
-





Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

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all

  • --


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