Template Revision 27
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
he Trenz Electronic TEI0006 is an Industrial grade module based on Intel® Cyclone 10 GX. Intel Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.
Refer to http://trenz.org/tei0006-info for the current online version of this manual and other available documentation.
Key Features
- Intel® Cyclone 10 GX Industrial [10CX220YF780I5G]
- Package: 780-FBGA
- Speed Grade: 5 (Fastest)
- Temperature: -40°C ~ 100°C
- SDRAM DDR3L Memory IC 8Gb, 800MHz
- 2x SPI Flash, 1 Gb
- 2x Transceiver Full Ethernet 64-QFN
- Programmable Oscillator
- EEPROM Memory, 2Kb
4x User LED
Board to Board (B2B):
- Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors
Power Supply:
Others:
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Intel® MAX 10, U18
- DC/DC convertor, U4...11
- SDRAM DDR3 Memory, U12...13
- User LEDs, D1...4
- Ethernet Tranciever, U2- U14
- SPI Flash Memory, U1- U3
- Intel® Cyclone 10 GX, U23
- EEPROM, U64
- Buffer, U16
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Programmed |
| DDR3 SDRAM | Not Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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The TEI00006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is potentially connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.
MODE Signal State | MSEL2 | MSEL1 | MSEL0 | Boot Mode |
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MSEL[2:0] | 0 | 1 | 0 | AS x4 / Fast | 0 | 1 | 1 | AS x1 / Standard | 0 | 0 | 0 | PS and FPP/ Fast | 0 | 0 | 1 | PS and FPP/ Standard |
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By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
Signals | Connected to | Description | Note |
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nCONFIG | 1.8V | Configuration trigger | From U18( Intel MAX 10) - Bank 3 | CONF_DONE | 1.8V | Configuration done | To U18( Intel MAX 10) - Bank 3 | nSTATUS | 1.8V | Configuration status | To U18( Intel MAX 10) - Bank 3 | DCLK | U1,U3 | Configuration clock | To U1(Flash Memory) From U18( Intel MAX 10) - Bank 3 | AS_DATA0...3 | U1 | Configuration data | To U1(Flash Memory) |
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Signal | B2B | Connected to | Note |
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PERST | J2-99 | Bank A2 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Intel Cyclone 10 GX | Bank 1C | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| Bank 1D | J3 | 24 Single ended (12 Diff pair) | 0.95V |
| Bank 2A | J2 | 1 Single ended | 1.8V | PERST | Bank 2J | J2 | 46 Single ended (23 Diff pair) | 1.8V |
| Bank 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| Bank 2L | J1 | 46 Single ended (23 Diff pair) | 3.0V |
| Bank 3A | - | - | 1.35V | VDD_DDR | Bank 3B | - | - | 1.35V | VDD_DDR | Intel Max 10 | Bank 1A | J2 | 8 Single ended | 3.3V |
| Bank 1B | J2 | 5 Single ended | 3.3V |
| Bank 2 | J3 | 2 Single ended | 1.8VIO |
| Bank 3 | - | - | 1.8VIO |
| Bank 5 | J2 | 4 Single ended | 3.3V |
| Bank 6 | J2 | 2 Single ended | 3.3V |
| Bank 8 | J2 | 25 Single ended | 3.3V |
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JTAG Interface
JTAG access to the TEI0006 SoM through B2B connector JM2.
JTAG Signal | B2B Connector | Note |
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TMS | J2-160 |
| TDI | J2-159 |
| TDO | J2-158 |
| TCK | J2-157 |
| JTAG_EN | J2-105 | Connected to 3.3V |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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MIO Pin | Connected to | B2B | Notes |
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MAX_IO1...22 | U18( Intel MAX 10) - Bank 8 | J2 |
| MAX_IO23...26 | U18( Intel MAX 10) - Bank 8 | J2 |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
Designator | Schematic | Connected to | Notes |
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U1
| NCSO | CSS Bank (Configuration Bank) | Used when you are not configuring using AS | DCK | DCLK | AS Configuration Clock | AS_DATA0 | CSS Bank (Configuration Bank) | AS Configuration Pin | AS_DATA1 | CSS Bank (Configuration Bank) | AS Configuration Data | AS_DATA2 | CSS Bank (Configuration Bank) | AS Configuration Data | AS_DATA3 | CSS Bank (Configuration Bank) | AS Configuration Data | U3 | QSPI_CS | Bank 2A |
| QSPI_CK | Bank 2A |
| QSPI_DATA0 | Bank 2A |
| QSPI_DATA1 | Bank 2A |
| QSPI_DATA2 | Bank 2A |
| QSPI_DATA3 | Bank 2A |
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EEPROM
Schematic | U64 Pin | B2B | Notes |
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I2C_SCL | SCL | J3-135 | Connected to Bank 2 of Intel Max 10 | I2C_SDA | SDA | J3-137 | Connected to Bank 2 of Intel Max 10 |
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Pins | I2C Address | Designator | Notes |
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I2C_SCL, I2C_SDA | 0x53 | U64 |
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DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0006 SoM has two 1 Gb volatile DDR3 SDRAM IC for storing user application code and data.
- Part number: IS43TR16512BL
- Supply voltage: 1.35V
- Speed: 800MHz
- Temperature: 0 ° C to 95 ° C
Ethernet
Signal Name | Connected to | B2B | Signal Description |
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PHY1_MDI0_P PHY1_MDI0_N | - - | J2-93 J2-91 |
| PHY1_MDI1_P PHY1_MDI1_N | - - | J2-87 J2-85 |
| PHY1_MDI2_P PHY1_MDI2_N | - - | J2-81 J2-79 |
| PHY1_MDI3_P PHY1_MDI3_N | - - | J2-75 J2-73 |
| ETH1_RST | Bank 2A | - | Connected to DVDDH Voltage | ETH1_MDC | Bank 2A | - | Connected to DVDDH Voltage | ETH1_MDIO | Bank 2A | - | Connected to DVDDH Voltage | ETH1_TXD0...7 | Bank 2A | - | Transfer | ETH1_RXD0...7 | Bank 2A | - | Recieve | ETH1_GTXCK | Bank 2A | - |
| ETH1_TXCLK | Bank 2A | - |
| ETH1_TXEN | - | - |
| ETH1_TXER | - | - |
| ETH1_RXCK | Bank 2A | - | Connected to GNG | ETH1_RXDV | Bank 2A | - | Connected to GNG | PHY1_INT | - | - | Connected to DVDDH Voltage | PHY1_LED1 | - | J2-69 | Connected to DVDDH Voltage | PHY1_LED2 | - | J2-67 | Connected to GNG | ETH1_CRS | Bank 2A | - |
| ETH1_XTAL_IN | ETH_CLKIN | - | From U21 (25MHz MEMS Oschillator) |
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Intel MAX 10
The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM.
Intel Max 10 Bank | Signals | Connected to | Description | Notes |
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Bank 1A | AIN0...7 | B2B- J2 |
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| Bank 1B | TCK, TDO, TMS, TDI, JTAGEN | B2B- J2 |
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| Bank 2 | PHY1_LED1 PHY1_LED2 | U23(Ethernet) U23(Ethernet) | Ethernet LED Ethernet LED | Tight to GND Tight to DVDDH | F_TCK, F_TDO, F_TDI, F_TMS | U23(Intel Cyclone 10 GX) - Bank CSS | Intel Cyclone 10 JTAG signals |
| I2C_SDA, I2C_SCL | U64(EEPROM) J3 (B2B) U14 (Programmable Oscillator) | I2C EEPROM signals |
| PLL_RST | U14 (Programmable Oscillator) | Oscillator reset signal |
| Bank 3 | nSTATUS, nCONFIG, CONF_DONE | U23(Intel Cyclone 10 GX) - Bank CSS | Intel Cyclone 10 Configuration signals |
| DCLK | U23(Intel Cyclone 10 GX) - Bank CSS U1(SPI Flash) | Intel Cyclone 10 Configuration clock from Flash memory |
| MSEL0...1 | U23(Intel Cyclone 10 GX) - Bank CSS | Intel Cyclone 10 Configuration mode signals |
| DEV_CLRN, INIT_DONE | U23(Intel Cyclone 10 GX) - Bank 2A |
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| M10_IO0...4 | U23(Intel Cyclone 10 GX) - Bank 2A |
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| Bank 5
| DIS_GROUP1...4 | T1...4 (N- Channel MOSFET) | Fast Discharching |
| MAX_IO23...26 | J2 (B2B) | Intel MAX 10 GPIO |
| PG_0.95V, EN_0.95V PG_1.8VIO, EN_1.8VIO | U7(Voltage Regulator) U7(Voltage Regulator) | Power control signals |
| Bank 6
| M10_CLK | U21(25MHz Oscillator) | Intel MAX 10 Clock |
| VADJ_VS0...2, VADJ_EN PG_1.35V, EN_1.35V PG_1.8V, EN_1.8V PG_VTT, EN_VTT PG_0V9, EN_0V9 | U11(Voltage Regulator) U8(Voltage Regulator) U5(Voltage Regulator) U9(Voltage Regulator) U4(Voltage Regulator) | Power control signals |
| PHY1_33LED1...2 | J2 (B2B) | Ethernet LED |
| LED_FP_1 LED_FP_2...4 | D1 D2...4 | User LEDs | Red LED Green LED | Bank 8 | M10_nSTATUS, M10_nCONFIG, M10_CONF_DONE | J2(B2B) | Intel MAX 10 configuration signals |
| MAX_IO1...22 | J2(B2B) | Intel MAX 10 GPIO |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D1 | Red | LED_FP_1 | Active high |
| D2 | Green | LED_FP_2 | Active high |
| D3 | Green | LED_FP_3 | Active high |
| D4 | Green | LED_FP_4 | Active high |
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Clock Sources
The TEI0006 has three MEMS oscillator and a programmable clock generator.
Designator | Description | Frequency | Note |
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U21 | MEMS Oscillator | 25MHz |
| U15 | MEMS Oscillator | 25MHz |
| U17 | MEMS Oscillator | 48MHz |
| U14 | Programmable Oscillator | Variable |
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Signals | Clock Type | In/ Out | Connected to | Frequency | Note |
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IN1_P IN1_N | Differential | In In | U15 (Oscillator) GND | 25 MHz |
| IN1..3 | Differential | In | J3(B2B) | Variable |
| XA XB | Differential |
| U17 (Oscillator) GND | 48 MHz |
| CLK0...4 | Differential | Out | J3(B2B) | 25MHz |
| REFCLK_EMIFP | Differential | Out | - | Variable |
| CLK6...7 | Differential | Out | U23 (Intel Cyclon 10 GX)- Bank 1D | Variable |
| CLK8...9 | Differential | Out | U23 (Intel Cyclon 10 GX)- Bank 1C | Variable |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage regulators can be enabled through U18(Intel MAX 10)- Bank 6.
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Voltage Level | Direction | Notes |
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VCCIO2K | 53, 54 | - | - | 1.8 V | Input |
| VADJ | 140,142 | - | - | 3.0 V | Output |
| VCCIO2J | - | 29,30 |
| 1.8 V | Input |
| 3.3V | - | 149,150 | - | 3.3 V | Output |
| 1.8_VIO | - | - | 139 | 1.8 V | Output |
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Bank Voltages
FPGA | FPGA Bank | Voltage Level | Notes |
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Intel Cyclone 10 GX | Bank 1C | 0.95 V |
| Bank 1D | 0.95 V |
| Bank 2A | 1.8 V |
| Bank 2J | 1.8 V |
| Bank 2K | 1.8 V | VCCIO2K | Bank 2L | 3.0 V |
| Bank 3A | 1.35 V | VDD_DDR | Bank 3B | 1.35 V | VDD_DDR | Intel Max 10 | Bank 1A | 3.3 V |
| Bank 1B | 3.3 V |
| Bank 2 | 1.8 V | 1.8VIO | Bank 3 | 1.8 V | 1.8VIO | Bank 5 | 3.3V |
| Bank 6 | 3.3V |
| Bank 8 | 3.3V |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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TEI0006 module has three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
- 3x REF-192552-02 (160-pins, 80 pins per row)
- ST5 Mates with SS5
Operating Temperature: -55°C ~ 125°C
Current Rating: 1.6 A per ContactNumber of Positions: ??
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit | Note |
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VCC | Core voltage power supply | -0.5 | 1.21 | V |
| VCCP | Periphery circuitry and transceiver fabric interface power supply | -0.5 | 1.21 | V |
| VCCERAM | Embedded memory power supply | -0.5 | 1.36 | V |
| VCCPT | Power supply for programmable power technology and I/O pre-driver | -0.5 | 2.46 | V |
| VCCIO | I/O buffers power supply | -0.5 | 4.10 | V | 3 V I/O |
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| -0.5 | 2.46 |
| LVDS I/O | VCCA_PLL | Phase-locked loop (PLL) analog power supply | -0.5 | 2.46 | V |
| VCCT_GXB | Transmitter power supply | -0.5 | 1.34 | V |
| VCCR_GXB | Receiver power supply | -0.5 | 1.34 | V |
| VCCH_GXB | Transceiver output buffer power supply | -0.5 | 2.46 | V |
| T_STG | Storage temperature |
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| °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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VCC | 0.87 | 0.93 | V | See Intel Cyclone 10 GX datasheet. | VCCP | 0.87 | 0.93 | V | See Intel Cyclone 10 GX datasheet. | VCCERAM | 0.87 | 0.93 | V | See Intel Cyclone 10 GX datasheet. | VCCPT | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | VCCPGM | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | VCCIO | 2.85 | 3.15 | V | See Intel Cyclone 10 GX datasheet. | VCCA_PLL | 1.71 | 1.89 | V | See Intel Cyclone 10 GX datasheet. | T_J | -40 | 100 | °C | See Intel Cyclone 10 GX datasheet. |
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Physical Dimensions
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes |
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2018-07-27 | 01 | - |
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Document Change History
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Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Revision | Contributor | Description |
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