Template Revision 2.9

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Cyclone10 LP Reference Kit is the world's first development board with a 55kLE Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.

Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Barrel Jack, J12
  2. RJ45 socket, J8...9
  3. D-Sub Connector, J11
  4. Push button(Reset), S7
  5. Grove connector, J5
  6. Under/Over Voltage Protecter, U9
  7. 7-segment LED, D11
  8. 1x6 pin header, J4
  9. 1x8 pin header, J2...3
  10. User Red LEDs, D2...9
  11. 8x User Red LEDs, D13...17
  12. 5x User Push buttons, S1- S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM memory, U3
  15. SDRAM memory, U10
  16. Voltage Regulator, U5- U7
  17. AD/DA Convertor, U2
  18. Pmod 2x6 SMD host socket, P1...6
  19. Intel®Cyclone 10 LP, U1
  20. Configuration memory, U5
  21. 1x10 pin header, J1
  22. EEEPROM, U15- U18- U20
  23. FTDI USB2 to JTAG/UART adapter, U14
  24. Micro USB 2.0 (receptacle) J10
  25. Push button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17- U19
  28. QSPI Flash memory, U12

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

QSPI Flash

Not programmed


EEPROMProgrammed

FTDI configuration

SDRAMNot programmed


PSRAMNot programmed
FTDI System Controller CPLDNot programmed
Configuration MemoryDemo Design


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Configuration mode has been set to AS (Active Serial) configuration. 

MODE Signal State

MSEL0MSEL1MSEL2MSEL3Connected to Boot Mode

MSEL[0:3]

0100Bank 6

AS (Active Serial)


RESET pin can be set through the push button S1.

Signal

Connected to Note

RESET

S7 (Push button)Connected to nCONFIG
RST_GPIOS2 (Push button)
EXT_RST

J3 (1x8 pin header)

Bank 2



Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 V
J4 (Pin header)6 Single ended3.3 V
Bank 2

J3 (Pin header)

1 Single ended3.3 V
P1 (PMod SMD host socket)8 Single ended3.3 V
P2 (PMod SMD host socket)8 Single ended3.3 V
J11 (VGA host Socket)14 Single ended3.3 V
Bank 6J5 (Grove connector)2 Single ended3.3 V
Bank 7P5 (PMod SMD host socket)8 Single ended3.3 V
P6 (PMod SMD host socket)8 Single ended3.3 V
Bank 8P3 (PMod SMD host socket)8 Single ended3.3 V
P4 (PMod SMD host socket)8 Single ended3.3 V


PMod SMD Host Socket

TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP (U1).

DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7


UART Interface

UART access to TEI0009 is available on 1x8 pin header J2. 

SchematicPin HeaderConnected to Voltage LevelNotes
TXDJ2Bank 13.3 V
RXDJ2Bank 13.3 V


Micro USB2.0 Connector

U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).

SchematicConnected to Voltage LevelNotes
USB_VBUSGND

D-U14 (FTDI FT2232)3.3 V
D+U14 (FTDI FT2232)3.3 V


RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .

PinSchematicETH1 PinETH2 PinNotes
TD+ETH_TX_PU17- TXPU19- TXP
CTETH_CTREF_TCT--Connected to GND
TD-ETH_TX_NU17- TXMU19- TXM
RD+ETH_RX_PU17- RXPU19- RXP
CTETH_CTREF_RCT--Connected to GND
RD-ETH_RX_NU17- RXMU19- RXM
LED GreenETH_LED0U17- NWAYENU19- NWAYEN
LED YellowETH_LED1U17- SPEEDU19- SPEED


D-Sub Connectors

TEI0009 is equipped with a D-Sub connector (Receptacle) which provides interface to Cyclone 10 LP through Bank 2.

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 2Red channel
VGA_GREENVGA_G0...3Bank 2Green channel
VGA_BLUEVGA_B0...3Bank 2Blue channel
VGA_RGB_HSYNCVGA_HSBank 2Horizontal sync
VGA_RGB_VSYNCVGA_VSBank 2Vertical sync


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
QSPI Flash memoryU12
SDRAM memoryU10
PSRAM memoryU3
7 Segment LEDD11
FTDI FT2232U14
Ethernet PHYU17, U19
Configuration MemoryU5
ADC/DACU2
EEPROMU15, U18, U20
User LEDsD2...D17
OscillatorsU16, U22


QSPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

There is a 64MBit QSPI Flash memory (U12) provided by Winbond which can be used to store data or configuration.

PinSchematicConnected to Notes
CSF_CSBank 7 
CLKF_CLKBank 7 
IO0...3F_IO0...3Bank 7 


SDRAM Memory

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0009 has 256 MBit volatile provided by Winbond , SDRAM IC(U10) for storing user application code and data. Up to 512 MBit SDRAM is possibleon other assembly option.

PSRAM Memory

The TEI0009 is integrated with 64Mbit Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. 

7 Segment LED

The TEI0009 has a LED 7 Segment- 4 Digit which is connected to Bank 6.

PinSchematicConnected to Notes
A/L1SEG_CABank 6 
B/L2SEG_CBBank 6 
C/L3SEG_CCBank 6
DSEG_CDBank 6
ESEG_CEBank 6
FSEG_CFBank 6
GSEG_CGBank 6
DPSEG_CDPBank 6
A1SEG_ANBank 6
A2SEG_AN4Bank 6
A3SEG_AN3Bank 6
A4SEG_AN2Bank 6
L1-L3SEG_AN1Bank 6


FTDI FT2232

The FTDI chip U14 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.

FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKBank 1JTAG interface
ADBUS1TDIBank 1
ADBUS2TDOBank 1
ADBUS3TMS

Bank 1

BDBUS0BDBUS0Bank 6
BDBUS1BDBUS1Bank 6
BDBUS2BDBUS2Bank 6
BDBUS3BDBUS3Bank 6
BDBUS4BDBUS4Bank 6
BDBUS5BDBUS5Bank 6
EECSEECSU15 (EEPROM)
EECLKEECLKU15 (EEPROM)
EEDATAEEDATAU15 (EEPROM)
OSCICK12MU16 (12MHz Oscillator)
DMD_NJ10 (Micro USB2.0)
DPD_PJ10 (Micro USB2.0)



Configuration Memory

On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.

Configuration Memory PinSignal Schematic NameConnected toNotes
DATA1AS_DATA0U1, Bank 1
Data out
DATA0AS_ASDOU1, Bank 1Data in
nCSAS_NCSU1, Bank 1chip select
DCLKAS_DCLK

U1, Bank 1

clock


Ethernet PHY

The TEI0009 is equipped with two Ethernet PHY (U19, U17) which are connected to two RJ45 connectors. 

Ethernet PHY PinSignal Schematic NamesETH 1ETH 2Note
TXD0...3ETH_TXD0...3Bank 5Bank 5
TXCETH_TXCBank 5Bank 5
TXENETH_TXENBank 5Bank 5
RXD0...3ETH_RXD0...3Bank 5Bank 5
RXC//B-CAST_OFFETH_RXCBank 5Bank 5
RXER/ISOETH_RXERBank 5Bank 5
INTRP//NAND_TreeETH_INTRPBank 5

Bank 5


XIETH_CLKINU22 (Oscillator)U22 (Oscillator)
MDCETH_MDCBank 5Bank 5
MDIOETH_MDIOBank 5Bank 5
COL/CONFIG0ETH_COLBank 5Bank 5
CRS/CONFIG1ETH_CRSBank 5Bank 5
RXDV/CONFIG2ETH_RXDVBank 5Bank 5
LED0/NWAYENETH_LED0

Bank 5

J8B (RJ45- Green LED)

Bank 5

J9B (RJ45-Green LED)


LED1/SPEEDETH_LED1

Bank 5

J8C (RJ45-Yellow LED)

Bank 5

J9B (RJ45-Yellow LED)


nRSTETH_RSTBank 5Bank 5
RXMETH_RX_NJ8 (RJ45)J9 (RJ45)
RXPETH_RX_PJ8 (RJ45)J9 (RJ45)
TXMETH_TX_NJ8 (RJ45)J9 (RJ45)
TXPETH_TX_PJ8 (RJ45)J9 (RJ45)


EEPROM

TEI0009 has three EEPROM, U15, U18 and U20. U15 is pre-programmed by FTDI FT2232H configuration.

DesignatorEEPROM PinSignal Schematic NamesConnected to Notes
U15CSEECSU14 (FTDI)
CLK|EECLKU14 (FTDI)
DIN/DOUTEEDATAU14 (FTDI)FTDI Configuration



DesignatorPinSchematicConnected to Grove HeaderNotes
U18, U20SCLI2C_SCLBank 6J5
SDAI2C_SDABank 6J5



I2C AddressDesignatorNotes
0x50U18
0x52U20


ADC/DAC

The TEI0009 module is equipped with 12bit ADC/DAC (U2).

PinsSchematicConnected toNotes

nRESET

ADDA_RSTNU1, Bank 2VREF_ADC
nSYNCADDA_SYNCU1, Bank 2
SCLKMCLKU1, Bank 2
SDIMSDIU1, Bank 2
SDOMSDOU1, Bank 2
VREF-U1, Bank 2External reference is 1 V to 3.3V
Internal reference is 2.5 V
IO0...5AIN0...5

U1, Bank 1

J4, Pin header



LEDs

SchematicDesignator ColorConnected toActive LevelNote
LED1...8D2...9RedBank 3High
LED_PB1D13...17RedBank 7High
CONF_DONED10RedBank 6Low


Push Buttons

Designator Connected toFunctionalityNote
S7RESETHigh
S2RST_GPIOHigh
S1, S3...6USER_BTN1...5User push buttonsconnected to bank 3


Clock Sources

DesignatorDescriptionFrequencyNote
U22MEMS Oscillator25 MHz
U16MEMS Oscillator12 MHz


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 1A for system startup is recommended.

Power Consumption

FPGATypical Current
Intel Cyclone 10 LP FPGATBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence

There is no power on sequence, After power on, all regulators will be enabled as you can see in the diagram below.




Voltage Monitor Circuit

There is a diod (D12) which protects the board from reverse polarity, Additionaly there is an Over/under voltage (IC) which protects the board from over voltage damages.




Power Rails


Connector Designator

VCC / VCCIO Schematic Name

Pin DirectionNotes
J33.3V2,4Out
5V5Out
J53.3V3Out


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 1VCCIO13.3V
Bank 2

VCCIO2

3.3V
Bank 3 VCCIO33.3V
Bank 4VCCIO43.3V
Bank 5VCCIO53.3V
Bank 6VCCIO63.3V


Bank 7VCCIO73.3V


Bank 8VCCIO83.3V


Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitNote
VIN Input supply voltage-5.05.0V
VCCIOI/O buffers power supply-0.53.75V
VCCINTCore voltage-0.51.8V
VCCD_PLLPLL digital power supply-0.51.8V
VCCAPhase-locked loop (PLL) analog power supply-0.53.75V
V_ANAnalog Input Voltage on ADC/DAC (U2)-0.33.6V
V_DIGDigital Input Voltage on ADC/DAC (U2)-0.33.6V
V_REF_INInternal Reference Voltage Voltage on ADC/DAC (U2)-0.33.6V
V_REF_EXExternal Reference Voltage Voltage on ADC/DAC (U2)-0.33.6V
T_STGStorage Temperature-3585°CSee LTC2623WC datasheet


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN 4.755.25V
VCCIO3.1353.465VSee Cyclone 10 LP datasheet.
VCCINT1.151.25VSee Cyclone 10 LP datasheet.
VCCD_PLL1.151.25VSee Cyclone 10 LP datasheet.
VCCA2.3752.625VSee Cyclone 10 LP datasheet.
V_AN03.3VSee  AD5592RBCPZ datasheet.
V_DIG03.3VSee  AD5592RBCPZ datasheet.
V_REF_IN13VSee  AD5592RBCPZ datasheet.
V_REF_EX2.452.55VSee  AD5592RBCPZ datasheet.
T_OP070°C

See SDRAM W9864G6JT datasheet


Physical Dimensions

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

if not available, set.


Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents


DateRevisionChangesDocument Link
2018-2-1901-REV01
2018-7-1802
  • Change J5 from SMD connector to GROVE connector
  • Connect clock 12 MHz to Bank 1
  • Connect I2C SLA/SDA to Bank 3
  • Remove SMA Coaxial straight J19,J20
  • Remove DIP Switch S1
  • Add 5 red LEDs
  • Add 2 Push buttons
  • Add 64 Mbit QSPI flash memory
  • Change SDRAM memory, 143 MHz to 166 MHz
  • Remove 10bit ADC
  • Remove 10bit DAC
  • Add 12bit DAC/ADC
  • Remove SMA Coaxial straight J19,J20
  • Remove SMA Coaxial straight J19,J20
  • Remove Tranciever USB
  • Remove DIP switch S2
  • Different Power Dependencies
  • Remove 24MHz Oscillator
  • Add 4x Pmod SMD host socket
REV02


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

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all

  • --


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