Module: TRM Name always "TE Series Name" +TRM Example: "TE0728 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM Example: "TEB0728 TRM"
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:
If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template:
Create DrawIO object here: Attention if you copy from other page, objects are only linked.
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Example
Comment
1
2
The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Figure_RH_HRN" for Hardware_Revision_Number
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
The Trenz Electronic TEI0006 is an industrial grade module based on Intel® Cyclone 10 GX. Intel® Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation of low cost FPGAs.
Refer to http://trenz.org/tei0006-info for the current online version of this manual and other available documentation.
Board to Board (B2B) Connection: Plug-on module with 3 x 160-pin Samtec Razor Beam (ST5) connectors
5 V Power Supply
Dimension: 80m x 60m
Block Diagram
add drawIO object here.
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .
Main Components
Notes :
Picture of the PCB (top and bottom side) with labels of important components
Add List below
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .
Intel® MAX 10, U18
DC/DC convertor, U4...11
SDRAM DDR3 Memory, U12 - U13
User LEDs, D1...4
Ethernet Transceiver, U2
SPI Flash Memory, U1 - U3
Intel® Cyclone 10 GX, U23
EEPROM, U64
Buffer, U16
Clock, U14
Initial Delivery State
Notes :
Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.
If there is no components which might have initial data ( possible on carrier) you must keep the table empty
Storage device name
Content
Notes
Quad SPI Flash
Not Programmed
EEPROM
Programmed
Ethernet MAC
DDR3 SDRAM
Not Programmed
Configuration Signals
Overview of Boot Mode, Reset, Enables.
The TEI0006 module can be configured using different modes. Mode selection can be done using MSEL[2:0]. MSEL2 is connected to GND so mode selection can be done using MSEL[1:0] which are connected to Bank 3 of Intel Max 10.
MODE Signal State
MSEL2
MSEL1
MSEL0
Boot Mode
MSEL[2:0]
0
1
0
AS / Fast
0
1
1
AS / Standard
0
0
0
PS and FPP / Fast
0
0
1
PS and FPP / Standard
By tying the CONF_DONE, NSTATUS, and NCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the NSTATUS pin, it resets the chain by pulling its NSTATUS pin low.
Signals
Connected to
Description
Note
NCONFIG
1.8V
Configuration trigger
From U18 (Intel MAX 10) - Bank 3
CONF_DONE
1.8V
Configuration done
To U18 (Intel MAX 10) - Bank 3
NSTATUS
1.8V
Configuration status
To U18 (Intel MAX 10) - Bank 3
DCLK
U1
Configuration clock
To U1 (Flash Memory)
From U18 (Intel MAX 10) - Bank 3
AS_DATA0...3
U1
Configuration data
From U1 (Flash Memory)
Signal
B2B
Connected to
Note
PERST
J2-99
Bank A2
Signals, Interfaces and Pins
Notes :
For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
SD
USB
ETH
FMC
...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA
FPGA Bank
B2B Connector
I/O Signal Count
Voltage Level
Notes
Intel Cyclone 10 GX
Bank 1C
J3
24 Single ended (12 Diff pair)
0.95V
GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P
Bank 1D
J3
24 Single ended (12 Diff pair)
0.95V
GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P
Bank 2A
J2
2 Single ended
1.8V
PERST, CLKUSR
Bank 2J
J2
46 Single ended (23 Diff pair)
VCCIO2J
Bank 2K
J1
46 Single ended (23 Diff pair)
VCCIO2K
Bank 2L
J1
48 Single ended (24 Diff pair)
VADJ up to 3 V
Bank 3A
-
-
1.35V
VDD_DDR
Bank 3B
-
-
1.35V
VDD_DDR
Intel Max 10
Bank 1A
J2
8 Single ended
3.3V
Bank 1B
J2
5 Single ended
3.3V
Bank 2
J3
2 Single ended
1.8VIO
Bank 3
-
-
1.8VIO
Bank 5
J2
4 Single ended
3.3V
Bank 6
J2
2 Single ended
3.3V
Bank 8
J2
24 Single ended
3.3V
JTAG Interface
JTAG access to the TEI0006 SoM through B2B connector J2. JTAGEN is pulled up to 3.3V and after power on, JTAG will be enabled.
JTAG Signal
B2B Connector
Note
TMS
J2-160
TDI
J2-159
TDO
J2-158
TCK
J2-157
JTAGEN
J2-105
Pulled up to 3.3V.
MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
MIO Pin
Connected to
B2B
Notes
MIO12...14
SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
J2
QSPI
MIO Pin
Connected to
B2B
Notes
MAX_IO1...20, 22
U18 (Intel MAX 10) - Bank 8
J2
MAX_IO23...26
U18 (Intel MAX 10) - Bank 5
J2
On-board Peripherals
Notes :
add subsection for every component which is important for design, for example:
Two 100 Mbit Ethernet Transciever PHY
USB PHY
Programmable Clock Generator
Oscillators
eMMCs
RTC
FTDI
...
DIP-Switches
Buttons
LEDs
Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection
Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.
The TEI0006 is equipped with two Micron SPI flash memory. On-board SPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
Designator
Schematic
Connected to
Notes
U1
NCSO
CSS Bank (Configuration Bank)
Used when you are not configuring using AS
DCK
DCLK
AS Configuration Clock
AS_DATA0
CSS Bank (Configuration Bank)
AS_DATA1
CSS Bank (Configuration Bank)
AS_DATA2
CSS Bank (Configuration Bank)
AS_DATA3
CSS Bank (Configuration Bank)
U3
QSPI_CS
Bank 2A
QSPI_CK
Bank 2A
QSPI_DATA0
Bank 2A
QSPI_DATA1
Bank 2A
QSPI_DATA2
Bank 2A
QSPI_DATA3
Bank 2A
EEPROM
Schematic
U64 EEPROM Pin
B2B
U18 Intel Max 10 Pin
Notes
I2C_SCL
SCL
J3-135
Bank 2 - K2
I2C_SDA
SDA
J3-137
Bank 2 - L2
Pins
I2C Address
Designator
Notes
I2C_SCL, I2C_SDA
0x53
U64
DDR3 SDRAM
Notes :
Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)
The TEI0006 SoM has two 1 GByte volatile DDR3 SDRAM IC provided by Integrated Silicon Solution Inc for storing user application code and data.
The TEI0006 is equipped with an Intel MAX 10 device which is a single-chip, non-volatile low-cost programmable logic device (PLD) to integrate the optimal set of system components. Intel MAX 10 (U18) is power and configuration controller on TEI0006 SoM.
Intel Max 10 Bank
Signals
Connected to
Description
Notes
Bank 1A
AIN0...7
B2B- J2
Bank 1B
TCK, TDO, TMS, TDI, JTAGEN
B2B- J2
Bank 2
PHY1_LED1
PHY1_LED2
Ethernet PHY, U2
Ethernet PHY, U2
Ethernet LED
Ethernet LED
Pulled-up to DVDDH.
Pulled-down to GND.
F_TCK, F_TDO, F_TDI, F_TMS
Intel Cyclone 10 GX (U23) - Bank CSS
Intel Cyclone 10 JTAG signals
I2C_SDA, I2C_SCL
EEPROM, U64
B2B, J3
Programmable Oscillator, U14
I2C EEPROM signals
PLL_RST
Programmable Oscillator, U14
Oscillator reset signal
Bank 3
NSTATUS, NCONFIG, CONF_DONE
Intel Cyclone 10 GX (U23) - Bank CSS
Intel Cyclone 10 Configuration signals
DCLK
Intel Cyclone 10 GX (U23) - Bank CSS
SPI Flash, U1
Intel Cyclone 10
Configuration clock from Flash memory
MSEL0...1
Intel Cyclone 10 GX (U23) - Bank CSS
Intel Cyclone 10
Configuration mode signals
DEV_CLRN, INIT_DONE
Intel Cyclone 10 GX (U23) - Bank 2A
M10_IO0...4
Intel Cyclone 10 GX (U23) - Bank 2A
Bank 5
DIS_GROUP1...4
N-Channel MOSFET, T1...4
Fast Discharching
MAX_IO23...26
B2B, J2
Intel MAX 10 GPIO
PG_0.95V, EN_0.95V
PG_1.8VIO, EN_1.8VIO
Voltage Regulator, U7
Voltage Regulator, U6
Power control signals
Bank 6
M10_CLK
25 MHz Oscillator, U21
Intel MAX 10 Clock
VADJ_VS0...2, VADJ_EN
PG_1.35V, EN_1.35V
PG_1.8V, EN_1.8V
PG_VTT, EN_VTT
PG_0V9, EN_0V9
Voltage Regulator, U11
Voltage Regulator, U8
Voltage Regulator, U5
Voltage Regulator, U9
Voltage Regulator, U4
Power control signals
PHY1_33LED1...2
B2B, J2
Ethernet LED
LED_FP_1
LED_FP_2...4
D1
D2...4
User LEDs
Red LED
Green LED
Bank 8
M10_nSTATUS, M10_nCONFIG
B2B, J2
Intel MAX 10 configuration signals
MAX_IO1...20, 22
B2B, J2
Intel MAX 10 GPIO
LEDs
Designator
Color
Connected to
Active Level
Note
D1
Red
LED_FP_1
Active high
D2
Green
LED_FP_2
Active high
D3
Green
LED_FP_3
Active high
D4
Green
LED_FP_4
Active high
Clock Sources
The TEI0006 has three crystal oscillator and a programmable clock generator.
Designator
Description
Frequency
Note
U21
Crystal Oscillator
25MHz
U15
Crystal Oscillator
25MHz
U17
Crystal Oscillator
48MHz
U14
Programmable Oscillator
Variable
Signals
Clock Type
In/ Out
Connected to
Frequency
Note
IN0_P
IN0_N
Differential
In
In
Oscillator, U15
GND
25 MHz
IN1..3
Differential
In
B2B, J3
Variable
XA
XB
Differential
Oscillator, U17
GND
48 MHz
CLK0
Differential
Out
Intel Cyclon 10 GX (U23)- Bank 2A
User
Default off
CLK1...4
Differential
Out
B2B, J3
User
Default off
REFCLK_EMIFP
Differential
Out
Intel Cyclon 10 GX (U23)- Bank 3B
User
Default off
CLK6...7
Differential
Out
Intel Cyclon 10 GX (U23)- Bank 1D
User
Default off
CLK8...9
Differential
Out
Intel Cyclon 10 GX (U23)- Bank 1C
User
Default off
Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
Power on-sequence
Power distribution
Voltage monitoring circuit
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .
Power Supply
Power supply with minimum current capability of 1 A for system startup is recommended.
Power Consumption
FPGA
Typical Current
Intel Cyclone 10 GX
TBD*
Intel MAX 10
TBD*
* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage regulators can be enabled through U18 (Intel MAX 10) - Bank 5 and 6.
Power Rails
Power Rail Name
B2B Connector
J1 Pin
B2B Connector
J2 Pin
B2B Connector
J3 Pin
Voltage Level
Direction
Notes
VIN
145, 147,149, 151, 153, 155, 157, 159
-
-
5 V
Input
VCCIO2K
53, 54
-
-
1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V
Input
VADJ
140,142
-
-
adjustable between 1.8 V - 3.0 V
Output
Voltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
VCCIO2J
-
29,30
-
1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V
Input
3.3V
-
149,150
-
3.3 V
Output
1.8_VIO
-
-
139
1.8 V
Output
Bank Voltages
FPGA
FPGA Bank
Voltage Level
Notes
Intel Cyclone 10 GX
Bank 1C
0.95 V
Bank 1D
0.95 V
Bank 2A
1.8 V
1.8VIO
Bank 2J
1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V
VCCIO2J
Bank 2K
1.2 V, 1.25 V, 1.35 V, 1.5 V, 1.8 V, 2.5 V or 3.0 V
VCCIO2K
Bank 2L
adjustable between 1.8 V - 3.0 V
Voltages according to EP53A8HQI datasheet
Bank 3A
1.35 V
VDD_DDR
Bank 3B
1.35 V
VDD_DDR
Intel Max 10
Bank 1A
3.3 V
Bank 1B
3.3 V
Bank 2
1.8 V
1.8VIO
Bank 3
1.8 V
1.8VIO
Bank 5
3.3V
Bank 6
3.3V
Bank 8
3.3V
Board to Board Connectors
This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
TEI0006 module has three Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
3x REF-192552-02 (160-pins, 80 pins per row)
ST5 Mates with SS5
Operating Temperature: -55°C to 125°C Current Rating: 1.6 A per Pin (2 pins powered)
Technical Specifications
Absolute Maximum Ratings
Symbols
Description
Min
Max
Unit
Note
VIN
Power supply
-0.3
6.0
V
Detemined by U10.
VCCIO - 3 V I/O
I/O buffers power supply
-0.5
4.10
V
Intel Cyclone 10 GX
VCCIO - LVDS I/O
I/O buffers power supply
-0.5
2.46
V
Intel Cyclone 10 GX
VADJ
Adjustable voltage
-0.5
4.10
V
Intel Cyclone 10 GX
T_STG
Storage temperature
-40
85
°C
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter
Min
Max
Unit
Reference Document
VIN
5.0
5.0
V
VCCIO
2.85
3.15
V
See Intel Cyclone 10 GX datasheet.
VADJ
2.85
3.15
V
VCCIO
Physical Dimensions
Module size: 60 mm × 80 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
PCB thickness: 1.7 mm
In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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