Template Revision 2.9

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Cyclone 10 LP Reference Kit is the world's first development board with a 55 kLE (Logic Elements) Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.

Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Power Jack, J12
  2. RJ45 Socket, J8...9
  3. D-Sub Connector, J11
  4. Push Button (Reset), S7
  5. Grove Connector, J5
  6. Undervoltage/Overvoltage Protector, U9
  7. 7-Segment LED, D11
  8. 1x6 Pin Header, J4
  9. 1x8 Pin Header, J2...3
  10. 8x User LEDs (Red), D2...9
  11. 5x User LEDs (Red), D13...17
  12. 5x User Push Buttons, S1 - S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM Memory, U3
  15. SDRAM Memory, U10
  16. Voltage Regulator, U4 - U7
  17. AD/DA Converter, U2
  18. 6x Pmod Host Socket, P1...6
  19. Intel® Cyclone 10 LP, U1
  20. Serial Configuration Memory, U5
  21. 1x10 Pin Header, J1
  22. EEPROM, U15 - U18 - U20
  23. FTDI USB 2 to JTAG/UART Converter, U14
  24. Micro USB 2.0, J10
  25. Push Button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17 - U19
  28. QSPI Flash Memory, U12

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

QSPI Flash (U12)

Not programmed


EEPROM (U15)Programmed

FTDI configuration

EEPROM (U18, U20)Not programmedExcept Ethernet MAC
SDRAM (U10)Not programmed


PSRAM (U3)Not programmed
Serial Configuration Memory (U5)Programmed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Configuration mode has been set to AS (Active Serial) configuration. 

MODE Signal State

MSEL0MSEL1MSEL2MSEL3Connected to Boot Mode

MSEL[0:3]

0100Bank 6

AS (Active Serial)



Signal

Connected to Note

RESET

S7, Push ButtonConnected to nCONFIG.


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the connectors:

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 V
J4 (Pin header)6 Single ended3.3 V
Bank 2

J3 (Pin header)

1 Single ended3.3 V
P1 (Pmod Host Socket)8 Single ended3.3 V
P2 (Pmod Host Socket)8 Single ended3.3 V
J11 (VGA Host Socket)14 Single ended3.3 V
Bank 6J5 (Grove Connector)2 Single ended3.3 V
Bank 7P5 (Pmod Host Socket)8 Single ended3.3 V
P6 (Pmod Host Socket)8 Single ended3.3 V
Bank 8P3 (Pmod Host Socket)8 Single ended3.3 V
P4 (Pmod Host Socket)8 Single ended3.3 V


Pmod Host Socket

TEI0009 has 6 Pmod 2x6 host sockets which are connected to Cyclon 10 LP (U1).

DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7



Pin Header

TEI0009 has 5 pin headers. The pin headers J1...4 are usable for Arduino modules, too.


Pin Header J1SignalsConnected to Notes
J1 - 1...6D8...13Bank 1
J1 - 7GND

J1 - 8AREFADC/DAC
J1 - 9D14_SDABank 1
J1 - 10D14_SCLBank 1



Pin Header J2SignalsConnected to Notes
J2 - 1D0_RXDBank 1
J2 - 2D1_TXDBank 1
J2 - 3...8D2...4Bank 1



Pin Header J3SignalsConnected to Notes
J2 - 1NC-
J3 - 23.3V3.3 V
J3 - 3EXT_RSTBank 2Pulled-up to 3.3 V
J3 - 43.3V3.3 V
J3 - 55V5 V
J3 - 6...7GNDGND
J2 - 8NC-



Pin Header J4SignalsConnected to Notes
J4 - 1...6AIN0...5FPGA Bank 1 and ADC/DAC



Pin Header J5SignalsConnected to Notes
J5 - 1I2C_SCLFPGA Bank 6 and EEPROM (U18, U20)Pulled-up to 3.3V.
J5 - 2I2C_SDAFPGA Bank 6 and EEPROM (U18, U20)Pulled-up to 3.3V.
J5 - 33.3V3.3 V
J5 - 4GNDGND


Micro USB 2.0 Connector

FTDI FT2232 (U14) can be accessed through micro USB 2.0 B connector (J10) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART or other standards.

RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively.

PinSchematicETH1 PinETH2 PinNotes
TD+ETH1_TX_P, ETH2_TX_PU17 - TXPU19 - TXP
CTETH1_CTREF_TCT, ETH2_CTREF_TCT--
TD-ETH1_TX_N, ETH2_TX_NU17 - TXMU19 - TXM
RD+ETH1_RX_P, ETH2_RX_PU17 - RXPU19 - RXP
CTETH1_CTREF_RCT, ETH2_CTREF_RCT--
RD-ETH1_RX_N, ETH2_RX_NU17 - RXMU19 - RXM
LED GreenETH1_LED0, ETH2_LED0U17 - LED0/NWAYENU19 - LED0/NWAYEN
LED YellowETH1_LED1, ETH2_LED1U17 - LED1/SPEEDU19 - LED1/SPEED


D-Sub Connector

TEI0009 is equipped with a D-Sub connector which provides interface to Cyclone 10 LP through Bank 2.

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 2Red Channel
VGA_GREENVGA_G0...3Bank 2Green Channel
VGA_BLUEVGA_B0...3Bank 2Blue Channel
VGA_RGB_HSYNCVGA_HSBank 2Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 2Vertical Sync


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
QSPI Flash MemoryU12
SDRAM MemoryU10
PSRAM MemoryU3
7-Segment LEDD11
FTDI FT2232U14
Ethernet PHYU17, U19
Serial Configuration MemoryU5
ADC/DACU2
EEPROMU15, U18, U20
User LEDsD2...D10, D13...D17
Push ButtonsS1...7
OscillatorsU16, U22


QSPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

There is a 64 MBit (8 MByte) QSPI Flash memory (U12) provided by Integrated Silicon Solution Inc. which can be used to store data or configuration. Up to 128 MBit (16 MByte) memory is available on other assembly option.

PinSchematicConnected to Notes
CSF_CSBank 7 
CLKF_CLKBank 7 
IO0...3F_IO0...3Bank 7 


SDRAM Memory

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0009 has 64 MBit (8 MByte) volatile memory provided by Integrated Silicon Solution Inc., SDRAM IC(U10) for storing user application code and data. Up to 512 MBit (64 MByte) SDRAM is available on other assembly option.

PSRAM Memory

The TEI0009 is integrated with 64 Mbit (8 MByte) Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. Up to 128 MBit (16 MByte) memory is available on other assembly option.

7-Segment Display

The TEI0009 has a 4-Digit-7-Segment LED display which is connected to Bank 6.

PinSchematicConnected to Notes
A/L1SEG_CABank 6 
B/L2SEG_CBBank 6 
C/L3SEG_CCBank 6
DSEG_CDBank 6
ESEG_CEBank 6
FSEG_CFBank 6
GSEG_CGBank 6
DPSEG_CDPBank 6
A1SEG_ANBank 6
A2SEG_AN4Bank 6
A3SEG_AN3Bank 6
A4SEG_AN2Bank 6
L1-L3SEG_AN1Bank 6


FTDI FT2232

The FTDI chip U14 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is routed to FPGA bank 6 and is usable for other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.

FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKBank 1JTAG interface
ADBUS1TDIBank 1
ADBUS2TDOBank 1
ADBUS3TMS

Bank 1

BDBUS0...7BDBUS0...7Bank 6
BCBUS0...7BCBUS0...7Bank 6
EECSEECSEEPROM, U15
EECLKEECLKEEPROM, U15
EEDATAEEDATAEEPROM, U15
OSCICK12M12 MHz Oscillator, U16
DMD_NMicro USB 2.0, J10
DPD_PMicro USB 2.0, J10



Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.

Configuration Memory PinSignal Schematic NameConnected toNotes
DATA1AS_DATA0U1, Bank 1

DATA0AS_ASDOU1, Bank 1
nCSAS_nCSU1, Bank 1
DCLKAS_DCLK

U1, Bank 1



Ethernet PHY

The TEI0009 is equipped with two Ethernet PHY (U17, U19) which are connected to two RJ45 (J8, J9) connectors. 

Ethernet PHY PinSignal Schematic Names (ETH1/ETH2)ETH 1ETH 2Note
TXD0...3ETH1_TXD0...3, ETH2_TXD0...3Bank 5Bank 5
TXCETH1_TXC, ETH2_TXCBank 5Bank 5
TXENETH1_TXEN, ETH2_TXENBank 5Bank 5
RXD0...3ETH1_RXD0...3, ETH2_RXD0...3Bank 5Bank 5
RXC/B-CAST_OFFETH1_RXC, ETH2_RXCBank 5Bank 5
RXER/ISOETH1_RXER, ETH2_RXERBank 5Bank 5
INTRP/nNAND_TreeETH1_INTRP, ETH2_INTRPBank 5

Bank 5


XIETH1_CLKIN, ETH2_CLKINOscillator, U22Oscillator, U22
MDCETH1_MDC, ETH2_MDCBank 5Bank 5
MDIOETH1_MDIO, ETH2_MDIOBank 5Bank 5
COL/CONFIG0ETH1_COL, ETH2_COLBank 5Bank 5
CRS/CONFIG1ETH1_CRS, ETH2_CRSBank 5Bank 5
RXDV/CONFIG2ETH1_RXDV, ETH2_RXDVBank 5Bank 5
LED0/NWAYENETH1_LED0, ETH2_LED0

RJ45 - Green LED, J8

RJ45 - Green LED, J9


LED1/SPEEDETH1_LED1, ETH2_LED1

RJ45 - Yellow LED, J8

RJ45 - Yellow LED, J9


nRSTETH1_RST, ETH2_RSTBank 5Bank 5
RXMETH1_RX_N, ETH2_RX_NRJ45, J8RJ45, J9
RXPETH1_RX_P, ETH2_RX_PRJ45, J8RJ45, J9
TXMETH1_TX_N, ETH2_TX_NRJ45, J8RJ45, J9
TXPETH1_TX_P, ETH2_TX_PRJ45, J8RJ45, J9


EEPROM

TEI0009 has three EEPROM, U15, U18 and U20. U15 is pre-programmed for the FTDI FT2232H configuration. U18 and U19 are used for the MAC address configuration.

DesignatorEEPROM PinSignal Schematic NamesConnected to Notes
U15CSEECSFTDI, U14
CLKEECLKFTDI, U14
DIN/DOUTEEDATAFTDI, U14



DesignatorPinSchematicConnected to Grove HeaderNotes
U18, U20SCLI2C_SCLBank 6J5
SDAI2C_SDABank 6J5



I2C AddressDesignatorNotes
0x50U18
0x51U20


ADC/DAC

The TEI0009 module is equipped with a 12-Bit ADC/DAC (U2).

PinsSchematicConnected toNotes

nRESET

ADDA_RSTNBank 2, U1
nSYNCADDA_SYNCBank 2, U1
SCLKMCLKBank 2, U1
SDIMOSIBank 2, U1
SDOMISOBank 2, U1
VREFAREFPin Header, J1External reference is 1 V to 3.3 V.
Internal reference is 2.5 V.
IO0...5AIN0...5

Bank 1, U1

Pin Header, J4


IO6AIN6Testpoint, TP1
IO7AIN7Testpoint, TP2


LEDs

SchematicDesignator ColorConnected toActive LevelNote
LED1...8D2...9RedBank 3High
LED_PB1...5D13...17RedBank 7High
CONF_DONED10RedBank 6Low
3.3VD1Green3.3VHigh


Push Buttons

SchematicDesignator Connected toFunctionalityNote
RESETS7Bank 1Reset
RST_GPIOS2Bank 4Reset/GPIO
USER_BTN1S3Bank 3User Push Button
USER_BTN2S4Bank 3User Push Button
USER_BTN3S5Bank 3User Push Button
USER_BTN4S6Bank 3User Push Button
USER_BTN5S1Bank 3User Push Button


Clock Sources

DesignatorDescriptionFrequencyNote
U22Crystal Oscillator25 MHz
U16Crystal Oscillator12 MHz


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

FPGATypical Current
Intel Cyclone 10 LP FPGATBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence

There is the following power-on sequence. The DCDC converter U7 enables the device U4 according to the diagram below.




Voltage Protection Circuit

There is a transient voltage suppression diode (D12) which protects the board from voltage spikes. Additionaly, there is an overvoltage / undervoltage protection device (U9) for board protection.




Power Rails


Connector Designator

VCCIO Schematic Name

Pin VCCDirectionNotes
J12VIN15 VIn
J33.3V2, 43.3 V Out
5V55 V Out
J53.3V33.3 V Out


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 1...8VCCIO1...83.3V


Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnitNote
VIN Input Supply Voltage (J12)
4.55.5V
AREFExternal Reference Voltage for ADC/DAC (J1 - 8)-0.33.6VOnly for input usage.
AIN0...5Input Voltage for ADC/DAC (J4)-0.33.6VOnly for input usage.
AIN6...7Input Voltage for ADC/DAC (TP1...2)-0.33.6VOnly for input usage.
EXT_RSTExternal Reset (J3 - 3)-0.54.2V
D0_RXD, D1_TXD, D2...7Arduino Interface (J2)-0.54.2VOnly for input usage.

D8...13, D14_SDA, D15_SCL

Arduino Interface (J1 - 1...6, 9...10)-0.54.2VOnly for input usage.
I2C_SCL, I2C_SDAI2C Interface (J5 - 1...2)-0.34.2VOnly for input usage.

P1_IO1...8, P2_IO1...8,

P3_IO1...8, P4_IO1...8,

P5_IO1...8, P6_IO1...8,

Pmod Interface (P1...6)-0.54.2VOnly for input usage.
CLK_INExternal FPGA Clock (J19)-0.54.2V
CLK_OUTClock / IO (J20)-0.54.2VOnly for input usage.
T_STGStorage Temperature-3585°CSee LTC2623WC datasheet


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN 4.755.25V

AREF13.3V

AIN0...50AREFV

AIN6...70AREFV

EXT_RST-0.53.6V

D0_RXD, D1_TXD, D2...7-0.53.6V

D8...13, D14_SDA, D15_SCL

-0.53.6V

I2C_SCL, I2C_SDA-0.33.3V

P1_IO1...8, P2_IO1...8,

P3_IO1...8, P4_IO1...8,

P5_IO1...8, P6_IO1...8,

-0.53.6V

CLK_IN-0.53.6V

CLK_OUT-0.53.6V

T_OP070°C

See SDRAM W9864G6JT datasheet



Physical Dimensions

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

if not available, set.


Trenz shop TEI0009 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents


DateRevisionChangesDocument Link
2018-2-1901----
2018-7-1802
  • Change J5 from SMD Connector to GROVE Connector
  • Change connection of 12 MHz clock from Bank 1 to Bank 6
  • Change connection of I2C SLA/SDA from Bank 3 to Bank 6
  • SMA Coaxial Connector J19, J20 not mounted
  • Change connection of CLK_IN/CLK_OUT from Bank 4 to Bank 8
  • Remove DIP Switch S1
  • Add 5 LEDs (red)
  • Add 2 Push Buttons
  • Add 64 Mbit QSPI Flash Memory
  • Change SDRAM Memory
  • Remove 10-Bit ADC
  • Remove 10-Bit DAC
  • Add 12-Bit ADC/DAC
  • Remove USB Transceiver
  • Remove 24 MHz Oscillator
  • Remove DIP Switch S2
  • Changed Power Supply Circuit
  • Add 4 Pmod Host Sockets
REV02


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Updated Figures

  • Updated Technical Specifications

v.40Pedram Babakhani
  • change list

--

all

  • --


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