Template Revision 2.5
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Note for Download Link of the Scroll ignore macro: |
Table of Contents |
Overview
The Trenz Electronic TEBT0808 is a test fixture for module TE0808(REV01, REV02) and TE0803(REV01) series.
Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.
Key Features
- Single 3.3V input (Direct modules power supply)
- Pin Header for TE0790 JTAG/UART Adapter
- 20 Pin ARM JTAG header (connected to MIO JTAG 0)
- 10 Pin I2C header for Silabs Clock Builder Field Programmer
- Done/Error/Status LEDs
- One PL GT with SMA Connectors
- One PS GT with SMA Connectors
- GT local loopback
- PL I/O loopbacks
- PS I/O loopbacks
- Boot Mode DIP Switch
- Power control switches to control TE080x power domains
- One pre-assembled TE0790 XMOD FTDI JTAG adapter
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Non-insulated Jack. J8-J7
- SMA Coaxial straight. J6- J9...15
- Surface Mount Schottky Barrier Rectifier. D1
- Box Headers, Straight/Angled J5-J16
- Board to Board Connector. J1...4
- Clock Oscillator, U2
- On-Board LEDs, D2...4
- DIP-Switch, S1...3
- XMOD JTAG Base, JX1
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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- | - | - |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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Boot mode can be set by DIP-Switch S1.
M3 | M2 | M1 | M0 | Bootmode Hex | Bootmode | Notes |
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ON | ON | ON | ON | 0xF | PS Main JTAG (TE0790 USB JTAG) |
| ON | ON | OFF | ON | 0xD | SPI Flash (dual parallel, 4bit x 2, 32bit Addressing) |
| ON | OFF | OFF | OFF | 0x8 | PJTAG(MIO29:26) |
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Signal | B2B | Note |
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PLL_RST | J2-89 |
| SRST_B | J2-96 | Connected to PJTAG0_SRST - J16 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
B2B Connector | Interfaces | Number of I/O | Notes |
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J1
| User I/O | 22 Single Ended, 11 Differential 8 Single Ended, 4 Differential 8 Single Ended, 4 Differential 8 Single Ended, 4 Differential 3 Single Ended | Connected to Bank 66 Connected to Bank 228 Connected to Bank 229 Connected to Bank 230 VCCO_66, PL_1V8 | J2
| Ethernet PHY | 32 Single Ended, 16 Differential 4 Single Ended, 16 Differential | Connected to Bank 505 Connected to Bank 128 | Control Signals | 15 Single Ended | PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE | Power Control Signal | 10 Single Ended | EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L | JTAG Interface | 7 Single Ended | TCK, TDI, TMS, TDO, MR, Rxd, Txd | WANNE2 | 2 Single Ended | PLL_SCL, PLL_SDA | Clock | 6 Single Ended, 3 Differential | CLK0, CLK7, CLK8 | J3
| User I/O | 12 Single Ended, 6 Differential 12 Single Ended, 6 Differential | Connected to Bank 48 Connected to Bank 47 | Clock | 6 Single Ended, 3 Differential | CLK228, CLK229, CLK230 | PJTAG Interface | 7 Single Ended | PJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO, | MIO | 27 Single Ended | MIO19..76 | UART | 2 Single Ended | TXD, RXD | Power pins | 4 Single Ended | PS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47 | J4 | User I/O | 48 Single Ended, 62 Differential 4 Single Ended | Connected to Bank 64 Connected to Bank 64 | Power pins | 4 Single Ended | VCCO_64, VCCO65 |
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XMOD JTAG
JTAG access to the TEBT080X is available through B2B connector JM2 using XMOD JTAG adapter TE0790 adapter.
JTAG Signal | B2B Connector | Notes |
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TMS | J2- 126 |
| TDI | J2- 122 |
| TDO | J2- 124 |
| TCK | J2- 120 |
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There is a DIP switch on TE0790 adapter which must be set accordingly.
DIP Switch | ON | OFF | Default | Description |
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1 | Normal mode | Adapter board CPLD update mode | ON | Update Mode JTAG access to SC CPLD only | 2 | Do not use (illegal setting) | Normal mode | OFF | Must be always in OFF state. | 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | User I/O Voltage | 4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
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The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches 3 and 4:
DIP Switch-3 | DIP Switch-4 | 3.3V (VCC) Pin 5 | VIO Pin 6 | Description |
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OFF | OFF | 3.3V from base (input**) | VIO from base (input**) | 3.3V (pin 5) and VIO (pin 6) sourced from base | OFF | ON | 3.3V from USB* (output**) | VIO from base (input**) | VIO sourced from base by Pin 6 | ON | OFF | 3.3V from base (input**) | 3.3V from base (input**) | VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V) | ON | ON | 3.3V from USB* (output**) | 3.3V from USB* (output**) | 3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V) |
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PJTAG
PJTAG access to the TEBT0808 is available through B2B connector JM3.
JTAG Signal | B2B Connector | Notes |
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TMS | J3- 94 |
| TDI | J3- 90 |
| TDO | J3- 92 |
| TCK | J3- 88 |
| SRST | J2- 96 | Connected to SRST_B |
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I2C Pin header
I2C signals can be accessed through pin header J5.
Signals | B2B Connector | Pin Header | Notes |
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PLL_SCL | J2- 90 | J5- 3 |
| PLL_SDA | J2- 92 | J5- 7 |
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SMA Coaxial
Designator | Signals | B2B Connector | Notes |
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J6 | B230_TX3_P | J1-2 |
| J9 | B230_RX3_N | J1-5 |
| J10 | B230_RX3_P | J1-3 |
| J11 | B230_TX3_N | J1-4 |
| J12 | B505_TX0_N | J2-67 |
| J13 | B505_TX0_P | J2-69 |
| J14 | B505_RX0_N | J2-70 |
| J15 | B505_RX0_P | J2-72 |
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Test Points
Test Point | Signals | B2B Connector | Notes |
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1 | DDR_1V2 | J2-135 |
| 2 | PG_PSGT | J2-82 |
| 3 | ERR_STATUS | J2-86 |
| 4 | PLL_FDEC | J2-94 |
| 5 | EN_LPD | J2-108 |
| 6 | EN_DDR | J2-112 |
| 7 | PG_PL | J2-104 |
| 8 | PG_PLL_1V8 | J2-80 |
| 9 | N_PSGT | J2-84 |
| 10 | ERR_OUT | J2-88 |
| 11 | EN_FPD | J2-102 |
| 12 | LP_GOOD | J2-106 |
| 13 | PG_FPD | J2-110 |
| 14 | PG_DDR | J2-114 |
| 15 | EN_PLL_PWR | J2-77 |
| 16 | PLL_FINC | J2-81 |
| 17 | PG_GT_R | J2-91 |
| 18 | EN_GT_R | J2-95 |
| 19 | EN_PL | J2-101 |
| 20 | EN_GT_L | J2-79 |
| 21 | PLL_SEL0 | J2-93 |
| 22 | PG_GT_L | J2-97 |
| 23 | INIT_B | J2-98 |
| 24 | IN1_P | J2-4 |
| 25 | PLL_SEL1 | J2-87 |
| 26 | PLL_LOLN | J2-85 |
| 27 | PLL_RST | J2-89 |
| 28 | DX_P | J2-119 |
| 29 | DX_N | J2-121 |
| 30 | IN1_N | J2-6 |
| 31 | B505_CLK0_P | J2-10 |
| 32 | B505_CLK0_N | J2-12 |
| 33 | B505_CLK1_P | J2-16 |
| 34 | B505_CLK1_N | J2-18 |
| 35 | B128_CLK1_P | J2-22 |
| 36 | B128_CLK1_N | J2-24 |
| 37 | CLK0_N | J2-1 |
| 38 | CLK0_P | J2-3 |
| 39 | CLK8_P | J2-7 |
| 40 | CLK8_N | J2-9 |
| 41 | CLK7_P | J2-13 |
| 42 | CLK7_N | J2-15 |
| 43 | IN2_P | J3-66 |
| 44 | IN2_N | J3-68 |
| 45 | B230_CLK1_N | J3-59 |
| 46 | B230_CLK1_P | J3-61 |
| 47 | B229_CLK0_N | J3-65 |
| 48 | B229_CLK0_P | J3-67 |
| 49 | PLL_3V3 | J3-152 |
| 50 | GND | J3-155 |
| 51 | PL_1V8 | J1-121 |
| 52 | PS_1V8 | J3-147 |
| 53 | SI_PLL_1V8 | J3-151 |
| 54 | PROG_B | J2-100 |
| 55...56 | GND | - |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
DIP Switch
There are thre DIP Switches, S1, S2, S3.
The Boot Mode can be set through DIP Switch S1, refer to BootMode table.
Signals | B2B | S1 switch | Notes |
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MODE0 | J2-109 | S1A |
| MODE1 | J2-107 | S1B |
| MODE2 | J2-105 | S1C |
| MODE3 | J2-103 | S1D |
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Control signals must be set using DIP Switch S2, S3.
Signals | B2B | S2 switch | Notes |
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EN_PSGT | J2-84 | S2A |
| EN_GT_R | J2-95 | S2B |
| EN_GT_L | J2-97 | S2C |
| EN_PLL_PWR | J2-77 | S2D | connected to PG_PL |
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Signals | B2B | S3 switch | Notes |
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EN_DDR | J2-112 | S3A |
| EN_LPD | J2-108 | S3B |
| EN_PL | J2-101 | S3C |
| EN_FPD | J2-102 | S3D |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D2 | Red | DONE | Low |
| D3 | Red | ERR_STATUS | Low |
| D4 | Red | ERR_OUT | Low |
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Clock Sources
Designator | Description | Frequency | Note |
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U2 | MEMS Oscillator | 125.00 MHz |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
2,0mm MC LB2 | Note |
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J7 | 3.3V direct modules power supply | J8 | GND |
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Power Consumption
Minimum current depends mainly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Input oower sourced directly the module, Only one Diode D1 is used for protection.
Power Rails
Power Rail Name | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | B2B JM4 Pin | Direction | Notes |
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3.3V | 151,153,155,157,159 | 140,142,144,154,156,158,160, 153,155,157,159 | 157,158,159,160 | - | Output | Carrier power supply to module power rails PL_DCDCIN. DCDCIN, LP_DCDC, GT_DCDC, PL_3V3V | VCCO_47 | - | - | 43, 44 | - | Output | Connected to 1.8 (SI_PLL_1V8) | VCCO_48 | - | - | 15,16 | - | Output | Connected to 1.8 (SI_PLL_1V8) | VCCO_64 | - | - | - | 58, 106 | Output | Connected to 1.8 (PL_1V8) | VCCO_65 | - | - | - | 69, 105 | Output | Connected to 1.8 (PL_1V8) | VCCO_66 | 90,120 | - | - | - | Output | Connected to 1.8 (PL_1V8) | PS_1V8 | - | 99, | 147, 148 | - | Input |
| PLL_3V3 | - | - | 152 | - | Output | 3.3V | PL_1_V8 | 121,121 | - | - | - | Input | 1.8V for PL Banks | SI_PLL_1V8 | - | - | 151 | - | Input |
| DDR 1V2 | - | 135 | - | - | Inout |
| PL_3V3 | - | - | 152 | - | Output | Connected to 3.3V | PSBAT | - | 125 | - | - | Output | 1.2V..1.5V, abs. max 2V |
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Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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Technical Specifications
Absolute Maximum Ratings
Symbols | Min | Max | Unit | Note |
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VIN | -0.3 | 4 | V | Note: VIN is connected directly to module, this is not considered here | Storage Temperatur | -40 | +85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Symbols | Min | Max | Unit | Note |
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VIN | 3,14 | 3.47 | V | Important, check also TRM of the connected module | Operating Temperatur |
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Physical Dimensions
PCB thickness: 1.6 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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2016-ß6-29 | 01 | - |
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Document Change History
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Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Revision | Contributor | Description |
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Disclaimer