Template Revision 2.11
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TE0802 is an evalution module.
Key Features
Note: 'Key Features' description: Important components and connector or other Features of the module → please sort and indicate assembly options |
- MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E
- SDRAM: LPDDR4-3733 8Gb 256Mx32
- Storages:
- SPI Flash 256Mb (32M x 8) 133 MHz
- microSD Card
- M.2 SSD PCIe
- Display Interfaces:
- DisplayPort
- VGA
- 4 Digit 7-Segment LED Display
- 8 LEDs
- Audio:
- Input:
- 5 User Buttons
- 8 Bit Slide Switches
- Reset Button
- User I/O:
- Communication:
- 1GB Ethernet RJ45
- USB 3.0 Host (Type A Connector)
- Debug
- Power
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- Xilinx Zynq UltraScale+ MPSoc, U14
- LPDDR4 SDRAM, U13
- M.2 Key M PCIe x1, U5
- SPI Flash Memory, U16
- EEPROM, U2, U18
- Oscillator, U15, U7, U19, U23, U43
- Clock Generator, U8
- Clock Generator Programming Connector, J14
- Grove Connector, J10
- Pmod Host Socket, J5...6
- Headphone Jack, J12
- D-Sub Connector, J7
- DisplayPort, J3
- RJ45 Socket, J4
- Ethernet PHY, U6
- USB Type A, J11
- USB 2.0 PHY, U22
- Micro USB 2.0 Type B, J8
- FTDI USB 2.0 to JTAG/UART Converter, U17
- microSD Card, J9
- Slide Switch, S1
- Push Button, BTN1...5
- DIP Switch, S7...8
- 4 Digit 7-Segment LED Display, D9
- 8x LEDs (Red), LED0...7
- Power Jack, J13
- Overvoltage/Undervoltage/Reverse Supply Protector, U12
- Power Management Integrated Circuit (PMIC), U1, U9
- Power Good LED (Green), D12
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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SPI Flash (U16) | Not programmed |
| EEPROM (U2) | Not programmed | Except Ethernet MAC | EEPROM (U18) | Programmed | FTDI Configuration | LPDDR4 SDRAM (U13) | Not programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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MODE Signal State | MODE0 | MODE1 | Boot Mode |
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MODE[1:0] | 0 | 0 | JTAG | MODE[1:0] | 0 | 1 | QSPI(24b) | MODE[1:0] | 1 | 0 | QSPI(32) | MODE[1:0] | 1 | 1 | SD0(2.0) |
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Signal | Connected to | Note |
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POR_B | BTN6, Push Button | Connected to nRESET |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
FPGA bank number and number of I/O signals connected to the connectors:
FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
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| J8, (Micro USB) |
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| J9, (Micro SD Card) |
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| J4, (RJ45) |
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| Bank 505 | J11, (USB 3.0) | 2 Differential Pairs | 0.85 V |
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| U5, (SSD M.2) |
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| Bank 505 | J3, (Display Port Connector) | 2 Differential Pairs | 0.85 V |
| Bank 26 | J7, (D-Sub Host Socket) | 2 Single Ended | 3.3 V |
| Bank 65, 66, | J7, (D-Sub Host Socket) | 12 Single Ended | 1.8 V |
| Bank 65 | J12, Headphone | 3 Single Ended | 1.8 V |
| Bank 500 | J10, (Grove Connector) | 2 Single Ended | 3.3 V |
| Bank 26 | J5 (Pmod Host Socket) | 8 Single Ended | 3.3 V |
| Bank 26 | J6 (Pmod Host Socket) | 8 Single Ended | 3.3 V |
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Pmod Host Socket
TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.
Designator | Signals | Connected to | Notes |
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J5 | PMOD_A0...7 | Bank 26 |
| J6 | PMOD_B0...7 | Bank 26 |
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Micro USB 2.0 Connector
FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.
RJ45 Connector
TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.
D-Sub Connector
TEI0802 is equipped with a D-Sub connector (J7).
Schematic | Corresponding Signals | Connected to | Notes |
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VGA_RED | VGA_R0...3 | Bank 65 | Red Channel | VGA_GREEN | VGA_G0...3 | Bank 65 | Green Channel | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync |
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Display Port Connector
TEI0802 is equipped with a Display Port connector (J3).
Schematic | Corresponding Signals | Connected to | Notes |
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DP_TX_L0_P/N | DP0_TX_P/N | Bank 505 |
| DP_TX_L1_P/N | DP1_TX_P/N | Bank 505 |
| DP_TX_AUX_P/N | DP_AUX_TX/RX | Bank 501 |
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Headphone Connector
TEI0802 is equipped with a headphone connector (J12).
Schematic | Corresponding Signals | Connected to | Notes |
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Micro SD Card Connector
TEI0802 is equipped with a micro SD card connector (J9).
Schematic | Corresponding Signals | Connected to | Notes |
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Grove Connector
TEI0802 is equipped with a grove connector (J10).
Schematic | Corresponding Signals | Connected to | Notes |
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USB Connector
TEI0802 is equipped with a USB connector (J11).
Schematic | Corresponding Signals | Connected to | Notes |
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SSD M.2 Connector
TEI0802 is equipped with a SSD M.2 connector (U5).
Schematic | Corresponding Signals | Connected to | Notes |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
MIO Pin | Schematic | U16 Pin | Notes |
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MIO0 | MIO0 | B2 | SPI_CLK | MIO1 | MIO1 | D2 | SPI_DQ1 | MIO2 | MIO2 | C4 | SPI_DQ2 | MIO3 | MIO3 | D4 | SPI_DQ3 | MIO4 | MIO4 | D3 | SPI_DQ0 | MIO5 | MIO5 | C2 | SPI_CS |
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LPDDR4 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC for storing user application code and data. The details depends on the assembly option.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
EEPROM
MIO Pin | Schematic | U?? Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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MIO8...9 | 0x50 | U2 |
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USB PHY
The TEI0802 is equipped with a USB PHY.
USB PHY Pin | Signal Schematic Names | USB | Note |
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Ethernet PHY
The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector.
Ethernet PHY Pin | Signal Schematic Names | ETH | Note |
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TXD0...3 |
| Bank |
| TXC |
| Bank |
| TXEN |
| Bank |
| RXD0...3 |
| Bank |
| RXC/B-CAST_OFF |
| Bank |
| RXER/ISO |
| Bank |
| INTRP/nNAND_Tree |
| Bank |
| XI |
| Oscillator, U |
| MDC |
| Bank |
| MDIO |
| Bank |
| COL/CONFIG0 |
| Bank |
| CRS/CONFIG1 |
| Bank |
| RXDV/CONFIG2 |
| Bank |
| LED0/NWAYEN |
| RJ45 - Green LED, J |
| LED1/SPEED |
| RJ45 - Yellow LED, J |
| nRST |
| Bank |
| RXM |
| RJ45, J |
| RXP |
| RJ45, J |
| TXM |
| RJ45, J |
| TXP |
| RJ45, J |
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FTDI FT2232
The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.
FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
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ADBUS0 | TCK | Bank | JTAG interface | ADBUS1 | TDI | Bank | ADBUS2 | TDO | Bank | ADBUS3 | TMS | Bank | BDBUS0 | FT_B_TX | Bank | UART | BDBUS1 | FT_B_RX | Bank | UART | EECS | EECS | EEPROM, U18 |
| EECLK | EECLK | EEPROM, U18 |
| EEDATA | EEDATA | EEPROM, U18 |
| OSCI | - | 12 MHz Oscillator, U19 |
| DM | D_N | Micro USB 2.0, J8 |
| DP | D_P | Micro USB 2.0, J8 |
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Clock Generator
The TEI0802 is equipped with a clock generator (U8).
Clock Generator Pin | Signal Schematic Names |
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Oscillators
Designator | Description | Frequency | Note |
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U43 | Clock for Clock Generator | 25 MHz |
| U15 |
| 33 MHz |
| U7 |
| 25 MHz |
| U23 | Clock for USB | 52 MHz |
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7-Segment Display
The TEI0802 has a 4-Digit-7-Segment LED display.
Pin | Schematic | Connected to | Notes |
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A/L1 | SEG_CA |
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| B/L2 | SEG_CB |
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| C/L3 | SEG_CC |
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| D | SEG_CD |
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| E | SEG_CE |
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| F | SEG_CF |
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| G | SEG_CG |
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| DP | SEG_CDP |
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| A1 | SEG_AN |
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| A2 | SEG_AN4 |
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| A3 | SEG_AN3 |
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| A4 | SEG_AN2 |
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| L1-L3 | SEG_AN1 |
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User LEDs
Schematic | Color | Connected to | Active Level | Note |
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LED0...7 | Red | Bank 65 | High |
| D12 | Green | U9, PMIC | High |
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Push Buttons
Schematic | Designator | Connected to | Functionality | Note |
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RESET |
| Bank | Reset |
| RST_GPIO |
| Bank | Reset/GPIO |
| USER_BTN_LEFT |
| Bank | User Push Button |
| USER_BTN_UP |
| Bank | User Push Button |
| USER_BTN_OK |
| Bank | User Push Button |
| USER_BTN_RIGHT |
| Bank | User Push Button |
| USER_BTN_DOWN |
| Bank | User Push Button |
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DIP Switch
Schematic | Color | Connected to | Active Level | Note |
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Switch
Schematic | Color | Connected to | Active Level | Note |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
| Schematic Name | | Notes |
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Bank 503 | +3.3V | 3.3 V |
| Bank 26 | +3.3V | 3.3 V |
| Bank 65 | +1.8V_PL | 1.8 V |
| Bank 500 | +3.3V | 3.3 V |
| Bank 501 | +3.3V | 3.3 V |
| Bank 502 | +1.8V_PS | 1.8 V |
| Bank 504 | +1.1V_LPDDR4 | 1.1 V |
| Bank 505 | +0.85V_MGTRAVCC +1.8V_MGTRAVTT | 0.85 V 1.8 V | ??? |
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Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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VIN | Input Supply Voltage (J13) | 4 | 5.5 | V |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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VIN | 4 | 5.5 | V |
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Physical Dimensions
Module size: 100 mm × 100 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1,48 mm
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Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
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Date | Revision | Contributor | Description |
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