Template Revision 2.11

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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  width: 100% !important;
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


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      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TE0802 is an evalution module.

Notes :

Key Features

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


MODE Signal State

MODE0MODE1Boot Mode

MODE[1:0]

00

JTAG

MODE[1:0]

01QSPI(24b)

MODE[1:0]

10QSPI(32)

MODE[1:0]

11SD0(2.0)




Signal

Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the connectors:

FPGA BankConnector I/O Signal CountVoltage LevelNotes

J8, (Micro USB)



J9, (Micro SD Card)



J4, (RJ45)


Bank 505J11, (USB 3.0)2 Differential Pairs0.85 V

U5, (SSD M.2)


Bank 505J3, (Display Port Connector)2 Differential Pairs0.85 V
Bank 26J7, (D-Sub Host Socket)2 Single Ended3.3 V
Bank 65, 66,J7, (D-Sub Host Socket)12 Single Ended1.8 V
Bank 65J12, Headphone3 Single Ended1.8 V
Bank 500J10, (Grove Connector)2 Single Ended3.3 V
Bank 26J5 (Pmod Host Socket)8 Single Ended3.3 V
Bank 26J6 (Pmod Host Socket)8 Single Ended3.3 V


Micro USB 2.0 Connector

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Micro SD Card Connector

TEI0802 is equipped with a micro SD card connector (J9).

SchematicCorresponding SignalsConnected toNotes













RJ45 Connector

TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.

PinSchematicETH PinNotes

































USB Connector

TEI0802 is equipped with a USB connector (J11).

SchematicCorresponding SignalsConnected toNotes













SSD M.2 Connector

TEI0802 is equipped with a SSD M.2 connector (U5).

SchematicCorresponding SignalsConnected toNotes













Display Port Connector

TEI0802 is equipped with a Display Port connector (J3).

SchematicCorresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NBank 505
DP_TX_L1_P/NDP1_TX_P/NBank 505
DP_TX_AUX_P/NDP_AUX_TX/RXBank 501


D-Sub Connector

TEI0802 is equipped with a D-Sub connector (J7).

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync


Headphone Connector

TEI0802 is equipped with a headphone connector (J12).

SchematicCorresponding SignalsConnected toNotes













Grove Connector

TEI0802 is equipped with a grove connector (J10).

SchematicCorresponding SignalsConnected toNotes













Pmod Host Socket

TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
QSPI Flash MemoryU16
SDRAM MemoryU13
EEPROMU18, U2
USB PHYU22
Ethernet PHYU6
FTDI FT2232HU17
Clock GeneratorU8
OscillatorsU43, U19, U15, U7, U23
7-Segment LEDD9
User LEDs

Push Buttons

DIP SwitchS1
Switch


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


LPDDR4 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC for storing user application code and data. The details depends on the assembly option.

EEPROM

MIO PinSchematicU?? PinNotes










MIO PinI2C AddressDesignatorNotes
MIO8...90x50U2


USB PHY

The TEI0802 is equipped with a USB PHY. 

USB PHY PinSignal Schematic NamesUSBNote

















































































Ethernet PHY

The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector. 

Ethernet PHY PinSignal Schematic NamesETHNote
TXD0...3
Bank
TXC
Bank
TXEN
Bank
RXD0...3
Bank
RXC/B-CAST_OFF
Bank
RXER/ISO
Bank
INTRP/nNAND_Tree
Bank
XI
Oscillator, U
MDC
Bank
MDIO
Bank
COL/CONFIG0
Bank
CRS/CONFIG1
Bank
RXDV/CONFIG2
Bank
LED0/NWAYEN

RJ45 - Green LED, J


LED1/SPEED

RJ45 - Yellow LED, J


nRST
Bank
RXM
RJ45, J
RXP
RJ45, J
TXM
RJ45, J
TXP
RJ45, J


FTDI FT2232

The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.

FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKBankJTAG interface
ADBUS1TDIBank
ADBUS2TDOBank
ADBUS3TMS

Bank

BDBUS0FT_B_TXBankUART
BDBUS1FT_B_RXBankUART
EECSEECSEEPROM, U18
EECLKEECLKEEPROM, U18
EEDATAEEDATAEEPROM, U18
OSCI-12 MHz Oscillator, U19
DMD_NMicro USB 2.0, J8
DPD_PMicro USB 2.0, J8


Clock Generator

The TEI0802 is equipped with a clock generator (U8). 

Clock Generator PinSignal Schematic Names
Note

















































































Oscillators

DesignatorDescriptionFrequencyNote
U43Clock for Clock Generator25 MHz
U15
33 MHz
U7
25 MHz
U23Clock for USB52 MHz


7-Segment Display

The TEI0802 has a 4-Digit-7-Segment LED display.

PinSchematicConnected to Notes
A/L1SEG_CA

B/L2SEG_CB

C/L3SEG_CC

DSEG_CD

ESEG_CE

FSEG_CF

GSEG_CG

DPSEG_CDP

A1SEG_AN

A2SEG_AN4

A3SEG_AN3

A4SEG_AN2

L1-L3SEG_AN1



User LEDs

SchematicColorConnected toActive LevelNote
LED0...7RedBank 65High
D12GreenU9, PMICHigh


Push Buttons

SchematicDesignator Connected toFunctionalityNote
RESET
BankReset
RST_GPIO
BankReset/GPIO
USER_BTN_LEFT
BankUser Push Button
USER_BTN_UP
BankUser Push Button
USER_BTN_OK
BankUser Push Button
USER_BTN_RIGHT
BankUser Push Button
USER_BTN_DOWN
BankUser Push Button



DIP Switch

SchematicColorConnected toActive LevelNote











Switch

SchematicColorConnected toActive LevelNote












Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence


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Power Rails


Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 503+3.3V3.3 V
Bank 26+3.3V3.3 V
Bank 65+1.8V_PL1.8 V
Bank 500+3.3V3.3 V
Bank 501+3.3V3.3 V
Bank 502+1.8V_PS1.8 V


Bank 504+1.1V_LPDDR41.1 V


Bank 505

+0.85V_MGTRAVCC

+1.8V_MGTRAVTT

0.85 V

1.8 V

???


Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)45.5V


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN45.5V


Physical Dimensions

Module size: 100 mm × 100 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1,48 mm

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .




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Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
-











Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


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Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Initial Release

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all

  • --


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