Template Revision 2.11

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TE0802 is an evalution module. Other assymbly options for the FPGA and the memory chips are available. Please ask for further information.

Notes :

Key Features

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


MODE Signal State

MODE0MODE1Boot Mode

MODE[1:0]

00

JTAG

MODE[1:0]

01---

MODE[1:0]

10QSPI(32)

MODE[1:0]

11SD0(2.0)




Signal

Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the connectors:

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503J8, (Micro USB)4 Single Ended3.3 VJTAG
Bank 500J8, (Micro USB)2 Single Ended3.3 VUART
Bank 500J9, (Micro SD Card)7 Single Ended3.3 V
Bank 502J4, (RJ45)14 Single Ended1.8 V
Bank 505J11, (USB 3.0)2 Differential Pairs0.85 V

Bank 505

U5, (SSD M.2)

2 Differential Pairs

0.85 V


Bank 501U5, (SSD M.2)5 Single Ended3.3 V
Bank 505J3, (Display Port Connector)2 Differential Pairs0.85 V
Bank 26J7, (D-Sub Host Socket)2 Single Ended3.3 V
Bank 65, 66,J7, (D-Sub Host Socket)12 Single Ended1.8 V
Bank 65J12, Headphone3 Single Ended1.8 V
Bank 500J10, (Grove Connector)2 Single Ended3.3 V
Bank 26J5 (Pmod Host Socket)8 Single Ended3.3 V
Bank 26J6 (Pmod Host Socket)8 Single Ended3.3 V


Micro USB 2.0

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Micro SD Card

TEI0802 is equipped with a micro SD card connector (J9).

SchematicConnected toNotes
SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45

TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.

PinSchematicETH PinNotes
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]


USB

TEI0802 is equipped with a USB connector (J11).

PinSchematicCorresponding SignalsConnected toNotes
D-USB0_D_NUSB0_DATA0...7MIO 52...63 FPGA Bank 502
D+USB0_D_PUSB0_DATA0...7MIO 52...63 FPGA Bank 502
StdA_SSRX-USB_RX2_N-FPGA Bank 505
StdA_SSRX+USB_RX2_P-FPGA Bank 505
StdA_SSTX-U3D2_NUSB_TX2_NFPGA Bank 505
StdA_SSTX+U3D2_PUSB_TX2_PFPGA Bank 505


SSD M.2

TEI0802 is equipped with a SSD M.2 connector (U5).

PinSchematicConnected toNotes
PERn0/SATA-B+

SSD_RX3_N

Pin M22, FPGA Bank 505
PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505
PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505
PERp0/SATA-A-SSD_TXC3_PPin M21, FPGA Bank 505
REFCLKN

SSD_RCLK_N

Pin 9, Clock Generator U8
REFCLKPSSD_RCLK_PPin 10, Clock Generator U8
DAS/DSS#SSD_DASMIO35, FPGA Bank 501
DEVSLPSSD_SLEEPMIO32, FPGA Bank 501
PERST#SSD_PERSTnMIO31, FPGA Bank 501
CLKREQ#SSD_CLKRQMIO33, FPGA Bank 501
PEWake#SSD_WAKEMIO34, FPGA Bank 501


Display Port

TEI0802 is equipped with a Display Port connector (J3).

SchematicCorresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NPin A19/A20, FPGA Bank 505
DP_TX_L1_P/NDP1_TX_P/NPin C19/C20, FPGA Bank 505
DP_TX_AUX_P/NDP_AUX_TX/RXMIO27, MIO30, FPGA Bank 501


D-Sub

TEI0802 is equipped with a D-Sub connector (J7).

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync


Headphone

TEI0802 is equipped with a headphone connector (J12).

SchematicConnected toNotes
JACKSNSPin F3, FPGA Bank 65
PWM_RPin F4, FPGA Bank 65
PWM_LPin E3, FPGA Bank 65


Grove

TEI0802 is equipped with a grove connector (J10).

SchematicConnected toNotes
Grove_SCL0MIO18, FPGA Bank 500
Grove_SDA0MIO19, FPGA Bank 500


Pmod

TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
Quad SPI Flash MemoryU16
LPDDR4 SDRAMU13
EEPROMU2, U18
USB ULPI PHYU22
Ethernet PHYU6
FTDI FT2232HU17
Clock GeneratorU8
OscillatorU7, U15, U19, U23, U43
7-Segment DisplayD9
User LEDLED0...7
Push ButtonBTN1...5
DIP SwitchS1, S7...8


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


LPDDR4 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.

EEPROM

MIO PinSchematicU2 PinNotes
MIO8Int_SCL1SCL
MIO9Int_SDA1SDA



MIO PinI2C AddressDesignatorNotes
MIO8...90x50U2



PinSchematicU18 PinNotes
CSEECS1FTDI
CLKEECLK2FTDI
DIN/DOEEDATA3/4FTDI



USB ULPI PHY

The TEI0802 is equipped with a USB ULPI PHY. 

USB PHY PinSignal Schematic NamesConnected toNote

DATA0

USB0_DATA0

MIO56, FPGA Bank 502
DATA1USB0_DATA1MIO57, FPGA Bank 502
DATA2USB0_DATA2MIO54, FPGA Bank 502
DATA3USB0_DATA3MIO59, FPGA Bank 502
DATA4USB0_DATA4MIO60, FPGA Bank 502
DATA5USB0_DATA5MIO61, FPGA Bank 502
DATA6USB0_DATA6MIO62, FPGA Bank 502
DATA7USB0_DATA7MIO63, FPGA Bank 502
DIRUSB0_DIRMIO53, FPGA Bank 502
NXTUSB0_NXPMIO55, FPGA Bank 502
STPUSB0_STPMIO58, FPGA Bank 502
RESETBUSB0_RST_NMIO38, FPGA Bank 501
CPENUSB0_VBUS_ENPin 1, U21 (Current-limited Power Switch)
VBUSVBUS

Pin 8, U21 (Current-limited Power Switch).

Pin 1, J11 (USB Connector)


IDUSB0_IDPulled-down to GND
DPUSB0_D_PPin 3, J11 (USB Connector)
DMUSB0_D_NPin 2, J11 (USB Connector)
REFCLKUSB0_RCLKPin 3, U23 (Oscillator)
CLKOUTUSB0_CLKMIO52, FPGA Bank 502


Ethernet PHY

The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector. 

Ethernet PHY PinSignal Schematic NamesETHNote
TXD0ETH_TXD0MIO65, FPGA Bank 502
TXD1ETH_TXD1MIO66, FPGA Bank 502
TXD2ETH_TXD2MIO67, FPGA Bank 502
TXD3ETH_TXD3MIO68, FPGA Bank 502
TX_CTRLETH_TXCTLMIO69, FPGA Bank 502
TX_CLKETH_CLKMIO64, FPGA Bank 502
MDIOETH_MDIOMIO77, FPGA Bank 502Pulled-up to +1.8V_PS.
MDCETH_MDCMIO76, FPGA Bank 502
MDIP[0]

PHY_MDI0_P

Pin2, J4 (RJ45)
MDIN[0]PHY_MDI0_NPin3, J4 (RJ45)
MDIP[1]

PHY_MDI1_P

Pin4, J4 (RJ45)
MDIN[1]PHY_MDI1_NPin5, J4 (RJ45)
MDIP[2]

PHY_MDI2_P

Pin6, J4 (RJ45)
MDIN[2]PHY_MDI2_NPin7, J4 (RJ45)
MDIP[3]

PHY_MDI3_P

Pin8, J4 (RJ45)
MDIN[3]PHY_MDI3_NPin9, J4 (RJ45)
LED[0]PHY_LED0LED, J4 (RJ45)
LED[1]PHY_LED1LED, J4 (RJ45)
CONFIG--Pulled-up to +1.8V_PS.
XTAL_INETH_XTAL_INPin 3, U7 (Oscillator)
RESETnETH_RSTMIO37, FPGA Bank 501Pulled-up to +1.8V_PS.
RX_CLKETH_RXCKMIO70, FPGA Bank 502
RX_CTRLETH_RXCTLMIO75, FPGA Bank 502
RXD[0]ETH_RXD0MIO71, FPGA Bank 502
RXD[1]ETH_RXD1MIO72, FPGA Bank 502
RXD[2]ETH_RXD2MIO73, FPGA Bank 502
RXD[3]ETH_RXD3MIO74, FPGA Bank 502


FTDI FT2232H

The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.

FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKPin H13, FPGA Bank 503JTAG Interface
ADBUS1TDIPin H12, FPGA Bank 503JTAG Interface
ADBUS2TDOPin J13, FPGA Bank 503JTAG Interface
ADBUS3TMS

Pin J12, FPGA Bank 503

JTAG Interface

BDBUS0FT_B_TXMIO10, FPGA Bank 500UART
BDBUS1FT_B_RXMIO11, FPGA Bank 500UART
EECSEECSPin 1, U18 (EEPROM)
EECLKEECLKPin 2, U18 (EEPROM)
EEDATAEEDATAPin 3/4, U18 (EEPROM)
OSCI-Pin 3, U19 (Oscillator)
DMD_NPin 2, J8 (Micro USB 2.0)
DPD_PPin 3, J8 (Micro USB 2.0)


Clock Generator

The TEI0802 is equipped with a clock generator (U8). 

Clock Generator PinSignal Schematic NamesConnected toNote
REFP-Pin 3, U43 (Oscillator)
REFSELREFSEL-Pulled-up to +3.3V.
RESETN/SYNCCLK_GEN_RESETPin B5, FPGA Bank 26Pulled-up to +3.3V.
EEPROMSELEEPROMSEL-Pulled-up to +3.3V.
SDA/GPIO2CLK_GEN_SDA

- (Default)

MIO9, FPGA Bank 500 (R185/196 required)

Pin 2, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

SCL/GPIO3CLK_GEN_SCL

- (Default)

MIO8, FPGA Bank 500 (R185/196 required)

Pin 3, J14 (Pin Header required)

Pulled-up to +3.3V. (Default)

Pulled-up to +3.3V.

Pulled-up to +3.3V.

OE/GPIO4--Pulled-up to +3.3V.

Y1P

CLK_Y1_P / CLK_DP_PPin G19, FPGA Bank 50527 MHz
Y1NCLK_Y1_N / CLK_DP_NPin G20, FPGA Bank 50527 MHz

Y2P

CLK_Y2_P / CLK_USB_PPin J19, FPGA Bank 50526 MHz
Y2NCLK_Y2_N / CLK_USB_NPin J20, FPGA Bank 50526 MHz

Y3P

CLK_Y3_P / CLK_PCIe_PPin L19, FPGA Bank 505100 MHz
Y3NCLK_Y3_N / CLK_PCIe_NPin L20, FPGA Bank 505100 MHz

Y4P

CLK_Y4_P / SSD_RCLK_PPin 55, U5 (M.2)100 MHz
Y4NCLK_Y4_N / SSD_RCLK_NPin 53, U5 (M.2)100 MHz


Oscillator

DesignatorSignal Schematic NamesConnected toDescriptionFrequencyNote
U7ETH_XTAL_INPin 34, U6 (Ethernet PHY)Clock for Ethernet25 MHz
U15PS_CLKPin H14, FPGA Bank 503Clock for FPGA33 MHz
U23USB_CLK / USB0_RCLKPin 26, U22 (USB PHY)Clock for USB52 MHz
U43-Pin 5, U8 (Clock Generator)Clock for Clock Generator25 MHz


7-Segment Display

The TEI0802 has a 4-Digit-7-Segment LED display.

PinSchematicConnected to Notes
A/L1CA / SEG_CAPin E4, FPGA Bank 65
B/L2CB / SEG_CBPin D3, FPGA Bank 65
C/L3CC / SEG_CCPin N5, FPGA Bank 65
DCD / SEG_CDPin P5, FPGA Bank 65
ECE / SEG_CEPin N4, FPGA Bank 65
FCF / SEG_CFPin C3, FPGA Bank 65
GCG / SEG_CGPin R5, FPGA Bank 65
DPCDP / SEG_CDPPin N3, FPGA Bank 65
A1SEG_AN1Pin A9, FPGA Bank 26
A2SEG_AN2Pin B9, FPGA Bank 26
A3SEG_AN3Pin A7, FPGA Bank 26
A4SEG_AN4Pin B6, FPGA Bank 26
L1-L3SEG_ANPin A8, FPGA Bank 26



User LED

SchematicColorConnected toActive LevelNote
LED0...7RedBank 65High
D12GreenU9, PMICHigh


Push Button

Designator SchematicConnected toFunctionalityNote
BTN_1USER_BTN_UPPin U2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_2USER_BTN_LEFTPin R1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_3USER_BTN_OKPin T1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_4USER_BTN_RIGHTPin U1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_5USER_BTN_DOWNPin T2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_6POR_B

Pin 38, U1 (PMIC),

Pin 38, U9 (PMIC),

Pin K12, FPGA Bank 503

Reset ButtonPulled-up to +3.3V.



DIP Switch

DesignatorSchematicConnected toFunctionalityNote
S1AMODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1BMODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1CUSER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1DUSER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND.
S7AUSER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7BUSER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7CUSER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7DUSER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8AUSER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8BUSER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8CUSER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8DUSER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence


TBD


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power Rails


Power Rail NameDirectionNotes
VINInSupply Voltage
+5VOutJ1...2
+3.3VOutJ14, J10


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 26+3.3V3.3 V
Bank 65+1.8V_PL1.8 V
Bank 66+1.8V_PL1.8 V
Bank 500+3.3V3.3 V
Bank 501+3.3V3.3 V
Bank 502+1.8V_PS1.8 V


Bank 503+3.3V3.3 V
Bank 504+1.1V_LPDDR41.1 V


Bank 505

+0.85V_MGTRAVCC

0.85 V



Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)-4050V


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN45.5V


Physical Dimensions

Module size: 100 mm × 100 mm.  Please download the assembly diagram for exact numbers.

PCB thickness: 1,48 mm

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz Shop TE0702 Overview Page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2019-04-2902
  • Added suppressor 1SMA5.0AT3G on power input
  • Changed OV and UV protection range
  • Changed VGA schematic
  • USB page: VBUS resistor changed on 1K
  • The revision has been renamed as TE0802-02-2AEV2-A

2018-10-1701Release


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Initial Release

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all

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