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Table of Contents |
Refer to https://wiki.trenz-electronic.de/display/PD/TE0745+TRM for online version of this manual and the rest of the available documentation. |
The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Industrial/Commercial/Expanded grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)
Additional assembly options are available for cost or performance optimization upon request.
Figure 1: TE0745-02 Block Diagram.
Figure 2: TE0745-02 SoC module.
Storage Device Name | Content | Notes |
---|---|---|
24AA025E48 EEPROM | User content, not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Not programmed | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Si5338 OTP NVM | Not programmed | OTP not re-programmable after delivery from factory |
Table 1: Initial delivery state.
The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signaling LVDS pairs are supported.
Bank | Type | B2B Connector | I/O Signal Count | LVDS Pairs Count | Bank Voltage | Notes |
---|---|---|---|---|---|---|
12 | HR | J1 | 50 | 24 | VCCIO_12 pins J1-54, J1-55 | Voltage range 1.2V to 3.3V |
13 | HR | J1 | 50 | 24 | VCCIO_13 pins J1-112, J1-113 | Voltage range 1.2V to 3.3V |
33 | HP | J3 | 50 | 24 | VCCIO_33 pins J3-115, J3-120 | Voltage range 1.2V to 1.8V |
34 | HP | J2 | 50 | 24 | VCCIO_34 pins J2-29, J2-30 | Voltage range 1.2V to 1.8V |
35 | HP | J2 | 50 | 24 | VCCIO_35 pins J2-87, J2-88 | Voltage range 1.2V to 1.8V |
500 | MIO | J2 | 5 | - | 1.8V | MIO0, MIO12 ... MIO15, user configurable I/O's on B2B |
501 | MIO | J3 | 12 | - | 1.8V | MIO40 ... MIO51, user configurable I/O's on B2B |
Table 2: Count, type and voltage range of SoC's PL and PS I/O banks pins available through B2B connectors.
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
For detailed information about the pin-out, please refer to the Pin-out Table.
The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
---|---|---|---|---|---|
0 | 112 | GTX |
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1 | 112 | GTX |
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2 | 112 | GTX |
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3 | 112 | GTX |
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4 | 111 1) | GTX |
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5 | 111 1) | GTX |
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6 | 111 1) | GTX |
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7 | 111 1) | GTX |
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Table 3: SoC's MGT lanes connections to the B2B connectors.
Below are listed MGT banks reference clock sources.
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
MGT_CLK0_P | 112 | B2B, J3-75 | MGTREFCLK0P_112, R6 | Supplied by the carrier board. |
MGT_CLK0_N | 112 | B2B, J3-77 | MGTREFCLK0N_112, R5 | Supplied by the carrier board. |
MGT_CLK1_P | 112 | U16, CLK0A | MGTREFCLK1P_112, U6 | On-module Si5338A. |
MGT_CLK1_N | 112 | U16, CLK0B | MGTREFCLK1N_112, U5 | On-module Si5338A. |
MGT_CLK2_P | 111 1) | B2B, J3-81 | MGTREFCLK0P_111, W6 | Supplied by the carrier board. |
MGT_CLK2_N | 111 1) | B2B, J3-83 | MGTREFCLK0N_111, W5 | Supplied by the carrier board. |
MGT_CLK3_P | 111 1) | U16, CLK3A | MGTREFCLK1P_111, AA6 | On-module Si5338A. |
MGT_CLK3_N | 111 1) | U16, CLK3B | MGTREFCLK1N_111, AA5 | On-module Si5338A. |
Table 4: MGT reference clock sources.
1) Note: MGT bank 111 not available at XC7Z030 Zynq SoC.
JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.
JTAG Signal | B2B Connector Pin |
---|---|
TCK | J1-143 |
TDI | J1-142 |
TDO | J1-145 |
TMS | J1-144 |
Table 5: JTAG interface signals.
JTAG_EN pin 148 in B2B connector J1 should be kept low or grounded for normal operation! |
Following special purpose pins are connected to System Controller CPLD:
Pin Name | Mode | Function | B2B Connector Pin | Default Configuration |
---|---|---|---|---|
JTAG_EN | Input | JTAG select | J1-148 | During normal operating mode the JTAG_EN pin should be in the low state for JTAG signals to be forwarded to the Zynq SoC. |
RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq chip. |
PS_SRST | Input | Reset | J2-152 | Low-active PS system-reset pin of Zynq chip. |
BOOTMODE_1 | Output | Boot mode | - | Control line which sets in conjunction with signal 'BOOTMODE' (B2B-pin J2-133) Permanent logic high in standard SC-CPLD firmware. |
PWR_PL_OK | Input | Power good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. |
PWR_PS_OK | Input | Power good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
EN_PL | Output | Enable signal | - | Low active Enable-signal for activating PL supply voltage. Permanent logic high in standard SC-CPLD firmware. |
MIO8 | Input | PS MIO | - | User I/O (pulled-up to PS_1.8V). |
MIO0 | Input | PS MIO | J2-137 | User I/O. |
RTC_INT | Input | Interrupt signal | - | Interrupt-signal from on-board RTC. |
LED | Output | LED control | - | Green LED D1, indicates SC-CPLD activity by blinking. |
Table 6: System Controller CPLD special purpose I/O pins.
On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
MIO | Signal Name | U14 Pin |
---|---|---|
1 | SPI-CS | C2 |
2 | SPI-DQ0/M0 | D3 |
3 | SPI-DQ1/M1 | D2 |
4 | SPI-DQ2/M2 | C4 |
5 | SPI-DQ3/M3 | D4 |
6 | SPI-SCK/M4 | B2 |
Table 7: MIO-pin assignment of the Quad SPI Flash memory IC.
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.
PHY Pin | ZYNQ PS | B2B | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
PHY LEDs | - | PHY_LED0: J2-144 | - |
PHY_LED2 / INTn: | - | J2-148 | Active low interrupt line. |
PHY_CLK125M | - | J2-150 | 125 MHz Ethernet PHY clock out. |
CONFIG | - | - | Permanent logic high. |
RESETn | MIO9 | - | Active low reset line. |
RGMII | MIO16 ... MIO27 | - | Reduced Gigabit Media Independent Interface. |
SGMII | - | - | Serial Gigabit Media Independent Interface. |
MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | Media Dependent Interface. |
Table 8: Ethernet PHY interface connections.
USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
PHY Pin | ZYNQ PS | B2B | Notes |
---|---|---|---|
ULPI | MIO28 ... MIO39 | - | Zynq USB0 MIO pins are connected to the PHY. |
REFCLK | - | - | 52MHz from on board oscillator (U33). |
REFSEL[0..2] | - | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz). |
RESETB | MIO7 | - | Low active USB PHY Reset (pulled-up to PS_1.8V). |
CLKOUT | MIO36 | - | Set to logic high to select reference clock (oscillator U33) operation mode. |
DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines. |
CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. |
VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics. |
ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device, leave floating. |
Table 9: USB PHY interface connections.
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
The I2C interface on B2B connector J2 has PS_3.3V as reference voltage and is connected to the Zynq SoC via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).:
B2B pin | Signal Schematic Name | Notes |
---|---|---|
J2-119 | I2C_33_SCL | 3.3V reference voltage |
J2-121 | I2C_33_SDA | 3.3V reference voltage |
Table 10: Pin assignment of the B2B I2C interface.
The on-module I2C interface works with reference voltage 1.8V:
PS Bank 500 | Signal Schematic Name | Notes |
---|---|---|
MIO 10 | I2C_SCL | 1.8V reference voltage |
MIO 11 | I2C_SDA | 1.8V reference voltage |
Table 11: MIO-pin assignment of the on-module I2C interface.
Except the on-module RTC (U24), all other on-module I2C slave devices are operating with the reference voltage PS_1.8V.
I2C addresses for on-module devices are listed in the table below:
I2C Device | I2C Address | Notes |
---|---|---|
Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA) | User programmable. | Configured as I2C by default. |
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA) | 0x70 | - |
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA) | 0x53 | - |
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL) | User programmable. | - |
RTC, U24 | 0x6F | - |
RTC RAM, U24 | 0x57 | - |
Table 12: Module's I2C-interfaces overview.
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).The boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5.
Following table describes how to set the control lines to configure the boot mode:
Boot Mode | MIO5 (BOOTMODE_1), SC CPLD | MIO4 (BOOTMODE), J2-133 | Note |
---|---|---|---|
JTAG | 0 | 0 | - |
QSPI Flash Memory | 1 | 0 | standard mode in current configuration. |
SD-Card | 1 | 1 | SD-Card on base board necessary. |
Table 13: Selectable boot modes.
In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. Basically MIO5 is set to 1 and JTAG is in cascade.
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
There is a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I2C-bus with address 0x70.
A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected between the Zynq module (master) and reference clock signal generator (slave).
Si5338A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN1 | CLKIN_P | B2B, J3-76 | Input | Reference input clock from base board. |
IN2 | CLKIN_N | B2B, J3-74 | Input | |
IN3 | Reference input clock. | Oscillator U21, pin 3 | Input | 25.000000 MHz oscillator, Si8008BI. |
IN4 | - | GND | Input | I2C slave device address LSB (0x70 default address). |
IN5 | - | Not connected. | Input | Not used. |
IN6 | - | GND | Input | Not used. |
CLK0A | MGT_CLK1_P | Zynq Soc U1, pin U6 | Output | MGT bank 112 reference clock. |
CLK0B | MGT_CLK1_N | Zynq Soc U1, pin U5 | Output | |
CLK1A | CLK1_P | B2B, J3-80 | Output | Reference clock output to base board. |
CLK1B | CLK1_N | B2B, J3-82 | Output | |
CLK2A | CLK2_P | B2B, J3-86 | Output | Reference clock output to base board. |
CLK2B | CLK2_P | B2B, J3-88 | Output | |
CLK3A | MGT_CLK3_P | Zynq Soc U1, pin AA6 | Output | MGT bank 111 reference clock. |
CLK3B | MGT_CLK3_N | Zynq Soc U1, pin AA6 | Output |
Table 14: Programmable quad PLL clock generator inputs and outputs.
The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
Clock Source | Schematic Name | Frequency | Clock Input Destination |
---|---|---|---|
SiTime SiT8008BI oscillator, U21 | - | 25.000000 MHz | Quad PLL clock generator U16, pin 3 |
SiTime SiT8008BI oscillator, U12 | PS_CLK | 33.333333 MHz | Bank 500 (MIO0 bank), pin B24 |
SiTime SiT8008BI oscillator, U33 | OTG-RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U32, pin 26 |
SiTime SiT8008BI oscillator, U9 | ETH_CLKIN | 25.000000 MHz | Gigabit Ethernet PHY U7, pin 34 |
Table 15: Clock sources overview.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Green | System Controller CPLD, bank 3, pin 5 | System main status LED, blinking indicates system activity |
D2 | Red | Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED remains OFF if System Controller CPLD can not power up the PL supply voltage. |
Table 16: LEDs of the module.
The maximum power consumption of a module mainly depends on the design which is running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input Pin | Typical Current |
---|---|
PL_VIN | TBD* |
PS_VIN | TBD* |
PS_3.3V | TBD* |
Table 17: Typical power consumption. *to be determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.
There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:
Figure 3: Power Distribution Diagramee
Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row). |
The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
Figure 4: Power-On Sequence
The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.
The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.
Figure 5: Voltage monitor circuit.
Voltages on B2B | B2B J1 Pin | B2B J2 Pin | B2B J3 Pin | Input/ | Note |
---|---|---|---|---|---|
PL_VIN | 147, 149, 151, 153, | - | - | Input | module supply voltage |
PS_VIN | - | 154, 156, 158 | - | Input | module supply voltage |
PS_3.3V | - | 160 | - | Input | module supply voltage |
VCCIO12 | 54, 55 | - | - | Input | high range bank I/O voltage |
VCCIO13 | 112, 113 | - | - | Input | high range bank I/O voltage |
VCCIO33 | - | - | 115, 120 | Input | high performance bank I/O voltage |
VCCIO34 | 29, 30 | - | Input | high performance bank I/O voltage | |
VCCIO35 | 87, 88 | - | Input | high performance bank I/O voltage | |
VBAT_IN | 146 | - | - | Input | RTC (battery-backed) supply voltage |
PS_1.8V | - | 130 | - | Output | internal 1.8V voltage level (Process System) |
PL_1.8V | - | - | 84,85 | Output | internal 1.8V voltage level (FPGA) |
Table 18: Power rails of the SoC module on B2B connectors.
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
0 (config) | VCCIO_0 | PL_1.8V, if R67 is equipped | - |
500 (MIO0) | PS_1.8V | 1.8V | - |
501 (MIO1) | PS_1.8V | 1.8V | - |
502 (DDR3) | 1.35V | 1.35V | - |
12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
13 HR | VCCIO_13 | User | HR: 1.2V to 3.3V |
33 HP | VCCIO_33 | User | HP: 1.2V to 1.8V |
34 HP | VCCIO_34 | User | HP: 1.2V to 1.8V |
35 HP | VCCIO_35 | User | HP: 1.2V to 1.8V |
Table 19: Range of SoC module's bank voltages.
Module Variant | Zynq SoC | SoC Junction Temperature | Operating Temperature Range |
---|---|---|---|
TE0745-02-30-1I | XC7Z030-1FBG676I | –40°C to +100°C | Industrial |
TE0745-02-35-1C | XC7Z035-1FBG676C | 0°C to +85°C | Commercial |
TE0745-02-45-1C | XC7Z045-1FBG676C | 0°C to +85°C | Commercial |
TE0745-02-45-2I | XC7Z045-2FBG676I | –40°C to +100°C | Industrial |
Table 20: Module variants.
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
PL_VIN | -0.3 | 5 | V | TI TPS720 data sheet |
PS_VIN | -0.3 | 7 | V | TI TPS82085 data sheet |
PS_3.3V | 3.135 | 3.465 | V | 3.3V nominal ± 5% Attention: PS_3.3V is directly connected to numerous |
VBAT supply voltage | -1 | 6.0 | V | ISL12020MIRZ data sheet |
PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | - |
I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | - |
GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.3 | 3.6 | V | MachX02 Family data sheet |
Storage temperature | -40 | +85 | °C | Limits of ISL12020MIRZ RTC chp. |
Storage temperature without the ISL12020MIRZ | -55 | +100 | °C | Limits of DDR3 memory chips. |
Table 21: Module absolute maximum ratings.
Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Notes | Reference Document |
---|---|---|---|---|---|
PL_VIN | 3.3 | 4.5 | V | - | TI TPS720 data sheet |
PS_VIN | 3.3 | 6.0 | V | - | TI TPS82085 data sheet |
PS_3.3V | 3.135 | 3.465 | V | - | 3.3V nominal ± 5% |
VBAT_IN supply voltage | 2.7 | 5.5 | V | - | ISL12020MIRZ data sheet |
PL I/O bank supply voltage for HR | 1.14 | 3.465 | V | - | Xilinx datasheet DS191 |
PL I/O bank supply voltage for HP | 1.14 | 1.89 | V | - | Xilinx datasheet DS191 |
I/O input voltage for HR I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 |
I/O input voltage for HP I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 |
GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 |
Voltage on Module JTAG pins | 3.135 | 3.6 | V | JTAG signals forwarded to Zynq module config bank 0 | MachX02 Family Data Sheet |
Table 22: Module recommended operating conditions.
Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Figure 6: Physical dimensions of the TE0745 SoC module.
Date | Revision | Notes | Link to PCN | Documentation Link |
---|---|---|---|---|
2016-10-11 | 02 |
| - | TE0745-02 |
2016-04-18 | 01 |
| - | TE0745-01 |
Table 23: Module hardware revision history.
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Figure 7: TE0745 module revision number.
Date | Revision | Contributors | Description |
---|---|---|---|
| |||
2019-06-14 | v.84 | John Hartfiel |
|
2018-04-11 | v.81 | John Hartfiel |
|
2017-11-14 | v.80 | John Hartfiel |
|
2017-11-13 | v.79 | Ali Naseri, Jan Kumann, John Hartfiel |
|
Table 24: Document change history.