Template Revision 2.6 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
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Table of contents |
Overview
Linux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).
Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
Key Features
Notes : - Add basic key futures, which can be tested with the design
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- Vivado 2018.3
- TEBF0808
- Linux
- USB
- ETH
- MAC from EEPROM
- PCIe
- SATA
- SD
- I2C
- RGPIO
- DP
- user LED access
- Modified FSBL for Si5338 programming
- Special FSBL for QSPI Programming
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Revision History
Notes : - add every update file on the download
- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2019-05-07 | 2018.3 | TE0803-StarterKit-vivado_2018.3-build_05_20190507093424.zip TE0803-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507093443.zip | John Hartfie | - new assembly variant
- TE Script update
- rework of the FSBLs
- SI5338 CLKBuilder Pro Project
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
| 2018-10-25 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_03_20181026141553.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_03_20181026141611.zip | John Hartfiel | | 2018-08-14 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_02_20180814103204.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip | John Hartfiel | | 2018-07-23 | 2018.2 | TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip | John Hartfiel | | 2018-07-12 | 2018.2 | TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip | John Hartfiel | - small petalinux changes
- IO renaming
- PL Design changes
- additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-05-17 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip | John Hartfiel | - new assembly variant
- solved Linux flash issue
| 2018-04-11 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip | John Hartfiel | - bugfix TE0803-01-04EG board part file
| 2018-02-13 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip | John Hartfiel | | 2018-02-06 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip | John Hartfiel | | 2018-02-05 | 2017.4 | TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip | John Hartfiel | - new assembly variant
- solved JTAG/Linux issue
| 2018-01-31 | 2017.4 | TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip | John Hartfiel | | 2018-01-18 | 2017.4 | TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip | John Hartfiel | |
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Release Notes and Know Issues
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround/Solution | To be fixed version |
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Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180517 update | USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is nessecary: - Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
| Solved with 20180205 update |
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Requirements
Software
Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vivado | 2018.3 | needed | SDK | 2018.3 | needed | PetaLinux | 2018.3 | needed | SI ClockBuilder Pro | --- | optional |
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Hardware
Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0803-ES1 | es1_2gb | REV01 | 2GB | 64MB | NA | NA | Not longer supported by vivado | TE0803-01-02EG-1E | 2eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA | TE0803-01-02CG-1E | 2cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA | TE0803-01-03EG-1E | 3eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA | TE0803-01-03CG-1E | 3cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA | TE0803-01-02EG-1EA | 2eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-02CG-1EA | 2cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-03EG-1EA | 3eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-03CG-1EA | 3cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-02-03EG-1EB | 3eg_4gb | REV02|REV01 | 4GB | 128MB | NA | NA | NA | TE0803-01-04CG-1EA | 4cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-04EV-1EA | 4ev_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-04EV-1E3 | 4ev_2gb | REV01 | 2GB | 128MB | NA | 1 mm connectors | NA | TE0803-01-04EG-1EA | 4eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-04CG-1EB | 4cg_2gb | REV01 | 2GB | 256MB | NA | NA | NA | TE0803-01-05EV-1EA | 5ev_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-01-05EV-1IA | 5ev_i_2gb | REV01 | 2GB | 128MB | NA | NA | NA | TE0803-02-04EV-1EB | 4ev_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0803-02-04EV-1E3 | 4ev_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0803-02-04EG-1E3 | 4eg_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0803-03-2AE11-A | 2cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-2BE11-A | 2eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-3AE11-A | 3cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-3BE11-A | 3eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-4AE11-A | 4cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-4BE11-A | 4eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-4BE21-L | 4eg_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0803-03-4BI21-A | 4eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0803-03-4DE11-A | 4ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-4DE21-L | 4ev_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0803-03-4GE21-L | 4eg_2_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA | TE0803-03-5DE11-A | 5ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA | TE0803-03-5DI21-A | 5ev_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
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Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Carrier Model | Notes |
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TEBF0808 | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
Type | Location | Notes |
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SI5338 | <design name>/misc/Si5338 | SI5338 Project with current PLL Configuration | init.sh | <design name>/sd/ | Additional Initialization Script for Linux |
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Prebuilt
Notes : - prebuilt files
- Template Table:
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- Create Project
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Note: - Programming and Startup procedure
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Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible - Copy image.ub on SD-Card
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to QSPI-Boot and insered SD.
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section TE0803 StarterKit#Programming
- Connect UART USB (JTAG XMOD)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect Sata Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
Vivado Hardware Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Control:
- LEDs: XMOD 2(without green dot) and HD LED are accessible.
- CAN_S
System Design - Vivado
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Block Design
PS Interfaces
Activated interfaces:
Type | Note |
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DDR |
|
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
CAN0 | EMIO |
I2C0 | MIO |
PJTAG0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 |
|
TTC0..3 |
|
GEM3 | MIO |
USB0 | MIO/GTP |
PCIe | MIO/GTP |
SATA | GTP |
DisplayPort | EMIO/GTP |
Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S SC16 J3:46 B26_L1_N
set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
# Audio Codec
#LRCLK J3:49
#BCLK J3:51
#DAC_SDATA J3:53
#ADC_SDATA J3:55
set_property PACKAGE_PIN L13 [get_ports LRCLK ]
set_property PACKAGE_PIN L14 [get_ports BCLK ]
set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
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Software Design - SDK/HSI
For SDK project creation, follow instructions from:
SDK Projects
Application
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2018.3 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2018.3 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
SDK template in ./sw_lib/sw_apps/ available.
zynqmp_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0803
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Activate:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenv dfu_alt_info " \
"image.ub ram $netstart 0x1e00000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
#define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#define CONFIG_ZYNQMP_EEPROM
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 0
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
#endif
|
Device Tree
/include/ "system-conf.dtsi"
/ {
};
/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/
/* default */
/* SD */
&sdhci1 {
// disable-wp;
no-1-8-v;
};
/*PCIE*/
&pcie {
phys = <&lane0 2 0 2 100000000>; //not recognized at the moment on linux
};
/* DP */
&zynqmp_dpsub {
phys = <&lane3 5 0 3 27000000>; //Xilinx default is 5 (UFS), 6 (DP) does not work
};
/* SATA */
&sata {
//phys = <&lane2 1 0 1 150000000>; //TE0808,TE0807
phys = <&lane2 1 0 0 150000000>; //TE0803
};
/* USB */
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
phy-names = "usb2-phy","usb3-phy";
phys = <&lane1 4 0 2 100000000>;
maximum-speed = "super-speed";
};
/* ETH PHY */
&gem3 {
phy-handle = <&phy0>;
phy0: phy0@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
/* QSPI */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* I2C */
&i2c0 {
i2cswitch@73 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
i2c@2 { // PCIe
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // i2c SFP
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 { // i2c SFP
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { // i2c EEPROM
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { // i2c FMC
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
si570_2: clock-generator3@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <78800000>;
};
};
i2c@7 { // i2c USB HUB
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
i2cswitch@77 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c-mux-idle-disconnect;
i2c@0 { // i2c PMOD
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 { // i2c Audio Codec
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/*
adau1761: adau1761@38 {
compatible = "adi,adau1761";
reg = <0x38>;
};
*/
};
i2c@2 { // i2c FireFly A
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // i2c FireFly B
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 { // i2c PLL
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { // i2c SC
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { // i2c
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c@7 { // i2c
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
|
Kernel
Start with petalinux-config -c kernel
Changes:
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
SI5338
File location <design name>/misc/Si5338/Si5338-*.slabtimeproj
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Document Revision | Authors | Description |
---|
| | | | 2018-10-26 | v.21 | John Hartfiel | | | v.19 | John Hartfiel | | | v.18 | John Hartfiel | | | v.16 | John Hartfiel | | | v.14 | John Hartfiel | - new assembly variant
- solved known issues
| | v.13 | John Hartfiel | | | v.12 | John Hartfiel | | | v.11 | John Hartfiel | - new assembly variant
- solved known issues
| 2018-01-29 | v.4 | John Hartfiel | | 2018-01-18 | v.3 | John Hartfiel | |
| All | |
|
|
Legal Notices