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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation


Table of contents

Overview

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General Design description
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Key Features

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  • PetaLinux
  • SD
  • ETH
  • I2C
  • RTC
  • FMeter
  • FSBL to enable I2C Buffer for PMIC(RTC) and external I2C
  • Special FSBL for QSPI programming

Revision History

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DateVivadoProject BuiltAuthorsDescription
2019-13-122018.2TE0724-test_board_noprebuilt-vivado_2018.2-build_04_20191212064015.zip
TE0724-test_board-vivado_2018.2-build_04_20191212064001.zip		ohn Hartfiel
  • bugfix IO constrains
2019-06-132018.2

TE0724-test_board-vivado_2018.2-build_04_20190613114927.zip
TE0724-test_board_noprebuilt-vivado_2018.2-build_04_20190613115049.zip

Oleksandr Kiyenko, John Hartfiel
  • add app to get access to EEPROM U10
2019-02-042018.2TE0724-test_board-vivado_2018.2-build_04_20190204111543.zip
TE0724-test_board_noprebuilt-vivado_2018.2-build_04_20190204111557.zip		John Hartfiel
  • Important Board Part File Update
    • change DDR3 to DDR3 Low Power
2018-08-292018.2TE0724-test_board_noprebuilt-vivado_2018.2-build_03_20180830170634.zip
TE0724-test_board-vivado_2018.2-build_03_20180830170621.zip		John Hartfiel
  • initial release

Release Notes and Know Issues

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IssuesDescriptionWorkaroundTo be fixed version
EEPROM U10 is not writeableWP is fix on on PCB Revisions, which shipped before 2019-06-13PCB can be patched, send request to Trenz Electronic support---

Requirements

Software

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SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed
PetaLinux2018.2needed

Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0724-02-10-1I10_1iREV021GB32MB

TE0724-02-20-120_1iREV021GB32MB

Design supports following carriers:

Carrier ModelNotes
TEB0724

Additional HW Requirements:

Additional HardwareNotes


Content

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
SDSoC<design name>/../SDSoC_PFMSDSoC Platform will be generated by TE Scripts or as separate download

Additional Sources

TypeLocationNotes



Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0724" possible
  4. Set Boot Mode to QSPI.
  5. Copy image.ub on SD-Card
  6. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card.
  2. Set Boot Mode to SD-Boot.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TE0724 Test Board#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI depending on programming option)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. EEPROM U10:
      Write: printf '\xaa' |eeprog /dev/i2c-0 0x50 -16 -f -x -w 7
      Read: eeprog /dev/i2c-0 0x50 -16 -f -x -r 0:32

Vivado HW Manager


System Design - Vivado

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Block Design

PS Interfaces

TypeNote
DDR
QSPIMIO
ETH0MIO
SD0MIO
UART1MIO
I2C1MIO
CAN0EMIO
GPIOMIO
TTC0..1EMIO
WDTEMIO


Constrains

Basic module constrains

#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constrain

# can
set_property PACKAGE_PIN T11 [get_ports CAN_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_tx]
set_property PACKAGE_PIN T10 [get_ports CAN_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_rx]
set_property PACKAGE_PIN U13 [get_ports {CAN_STBY[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CAN_STBY[0]}]
# led
set_property PACKAGE_PIN U12 [get_ports {LED_RG[0]}]
set_property PACKAGE_PIN W13 [get_ports {LED_RG[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_RG[*]}]
# CLK
set_property PACKAGE_PIN U14 [get_ports {PHY_CLK125M[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PHY_CLK125M[0]}]
# PWR GPIO
set_property PACKAGE_PIN T12 [get_ports {PWR_GPIO01[0]}]
set_property PACKAGE_PIN U15 [get_ports {PWR_GPIO01[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PWR_GPIO01[*]}]
# TEB0724 Button
set_property PACKAGE_PIN Y19 [get_ports {TEB0724_BUTTON_S24[0]}]
set_property PACKAGE_PIN Y18 [get_ports {TEB0724_BUTTON_S24[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TEB0724_BUTTON_S24[*]}]
# TEB0724 LED
set_property PACKAGE_PIN P18 [get_ports {TEB0724_ULED[0]}]
set_property PACKAGE_PIN N17 [get_ports {TEB0724_ULED[1]}]
set_property PACKAGE_PIN R17 [get_ports {TEB0724_ULED[2]}]
set_property PACKAGE_PIN R16 [get_ports {TEB0724_ULED[3]}]
set_property PACKAGE_PIN Y14 [get_ports {TEB0724_ULED[4]}]
set_property PACKAGE_PIN W14 [get_ports {TEB0724_ULED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {TEB0724_ULED[*]}]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

Source location: \sw_lib\sw_apps

zynq_fsbl

TE modified 2018.2 FSBL

Functions:

Changes:

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

hello_te0724

Hello World App in Endless loop.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};

/* default */

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/* ETH PHY */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};


/* I2C */
// EEPROM: 0x50. 0x53

//pmic
&i2c1 {
     pmic0: da9062@58 {
        compatible = "dlg,da9062";
        reg = <0x58>;    
         interrupt-parent = <&gpio0>;
        interrupts = <0 8>;
        interrupt-controller;
        rtc {
            compatible = "dlg,da9062-rtc";
        };
    };
};

Kernel

Activate:

Deactivate:

Rootfs

Activate:

Applications

eeprog

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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No additional software is needed.


Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionAuthorsDescription



  • Bugfix IO constrains
2019-06-13v.7John Hartfiel
  • Update Design Files
  • Notes U10 access
2019-02-04v.6John Hartfiel
  • Update Design Files

2018-08-30

v.5John Hartfiel
  • 2018.2 release
2018-08-29v.1


  • Initial release

All


Legal Notices