Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TE0821-01-3BI21FA is a powerful 4 x 5 cm MPSoC module with a Xilinx Zynq UltraScale + ZU3EG. In addition, the module is equipped with a 2 GB DDR4 SDRAM chip, 128 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. Robust high-speed connectors provide a large number of inputs and outputs.

This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0821-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .







Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. B2B connector Samtec Razor Beam, JM1
  9. Green User LED, D2
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

QSPI Flash Memory

Not programmed


eMMC Memory

Not programmed


Programmable Clock GeneratorNot programmed
CPLD (LCMXO2-256HC)SC0820-02 QSPI Firmware


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

MODE Pin

Boot Mode
Low

QSPI

HighSD Card




Signal

B2BI/ONote

EN

JM1-28InputCPLD Enable Pin


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
24HDJM224x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
25HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
26HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
44HDJM224x I/O, 12x  LVDS PairsVariableMax voltage 3.3V
65

HP

JM2

18x I/O, 9x LVDS Pairs

VariableMax voltage 1.8V

65

HP

JM3

16x I/O, 8x LVDS Pairs

Variable

Max voltage 1.8V
505GTRJM316x I/O, 8x LVDS Pairs-4x lanes
505GTR CLKJM31x Diff Clock-

501

MIO

JM1

15 I/O

3.3V




JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

JTAG Signal

B2B Connector

Note
TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99 
JTAGENJM1-89Pulled Low: Xilinx Zynq UltraScale+ MPSoC
Pulled High: Lattice MachXO CPLD


MGT Lanes

There are 4x MGT Lanes connected to FPGA Bank 505-GTR.

Lane

SchematicB2BNote
0
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27

1
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21

2
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15

3
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9


Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

PinSchematicConnected toNote
MDIP0...3

PHY_MDI0...3

B2B, JM1


MDC

ETH_MDC

MIO76


MDIOETH_MDIOMIO77
S_INS_INB2B, JM3
S_OUTS_OUTB2B, JM3
TXD0..3ETH_TXD0...3MIO65...68
TX_CTRLETH_TXCTLMIO69
TX_CLKETH_TXCKMIO64
RXD0...3ETH_RXD0...3MIO71...74
RX_CTRLETH_RXCTLMIO75
RX_CLKETH_RXCKMIO70
LED0...2PHY_LED0...2FPGA Bank 66
RESETnETH_RSTMIO24


MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK

J2QSPI



MIO PinConnected toB2BNotes
0...5QSPI Flash, U7-SPI Flash
7...12QSPI Flash, U17-SPI Flash
13...23eMMC, U6

24ETH Transceiver, U8-ETH_RST
25USB2.0 Transceiver, U18-OTG_RST
26...33User MIOJM1
34...37N.C-N.C
38...39EEPROM, U25-I2C_SDA/SCL
40...45N.C
N.C
46...51SD CardJM1
52...63USB2.0 Transceiver, U18-
63...77Ethernet Transceiver, U8-


Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Test PointSignalConnected toNotes
1I2C_SCLEEPROM, U25
2I2C_SDAEEPROM, U25
3SRST_BFPGA Bank 503PSCONFIG
4PS_CLKFPGA Bank 503PSCONFIG
5PROG_BFPGA Bank 503PSCONFIG
6INIT_BFPGA Bank 503PSCONFIG
7DONERed LED, D1
8PS_LP0V85Voltage Regulator, U12
9DDR_2V5Voltage Regulator, U4
10PS_AVCCVoltage Regulator, U9
11DDR_1V2Voltage Regulator, U15
12PS_AVTTVoltage Regulator, U3
13PS_FP0V85Voltage Regulator, U26
14POR_BVoltage Translator, U19
15PS_PLLVoltage Regulator, U23
16PL_VCCINTVoltage Regulator, U5


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
QSPI FlashU7, U17
EEPROMU25
DDR4 SDRAMU2,U3
GigaBit EthernetU8
USB2.0 TransceiverU18
OscillatorsU32, U14, U11
Programmable Clock GeneratorU25
CPLDU21
LEDsD1...3


Quad SPI Flash Memory

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TE0821 is equipped with dual Flash Memory, U7, U17.

PinSchematicNotes
U7 PinU17 Pin
nCSMIO5MIO7
CLKMIO0MIO12
DI/IO0MIO4MIO8
DO/IO1MIO1MIO9
nHOLD/IO3MIO3MIO11
WP/IO2MIO2MIO10



EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

MIO PinSchematicU25 PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL



MIO PinI2C AddressDesignatorNotes
MIO38...390x50U25


LEDs

DesignatorColorConnected toActive LevelNote
D1RedDONELow
D2GreenUSR_LEDHigh
D3RedERR_OUTHigh
D4GreenERR_STATUSHigh


DDR4 SDRAM

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

GigaBit Ethernet

PinSchematicConnected toNote
MDIP0...3

PHY_MDI0...3

B2B, JM1


MDC

ETH_MDC

MIO76


MDIOETH_MDIOMIO77
S_INS_INB2B, JM3
S_OUTS_OUTB2B, JM3
TXD0..3ETH_TXD0...3MIO65...68
TX_CTRLETH_TXCTLMIO69
TX_CLKETH_TXCKMIO64
RXD0...3ETH_RXD0...3MIO71...74
RX_CTRLETH_RXCTLMIO75
RX_CLKETH_RXCKMIO70
LED0...2PHY_LED0...2FPGA Bank 66
RESETnETH_RSTMIO24


Clock Sources

DesignatorDescriptionFrequencyNote
U11MEMS Oscillator25 MHz
U14MEMS Oscillator52 MHz
U32MEMS Oscillator80 MHz


Programmable Clock Generator

There is a programmable clock generator on-board (U10) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??.  The I2C Address is 0x70 or 0x71.

U25 Pin
SignalConnected toDirectionNote

IN0..1

CLK_INJM3IN
IN2CLK_25MOscillator, U11IN
SCLI2C_SCLEEPROM,U25INOUT
SDAI2C_SDAEEPROM,U25INOUT
CLK0CLK0JM3OUT
CLK1B505_CLK3FPGA Bank 505IN
CLK2B505_CLK1FPGA Bank 505IN
CLK3CLK3_N
IN


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*
3.3VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence




Power Rails

Power Rail Name

B2B JM1 Pin

B2B JM2 Pin

Direction

Notes
VIN

1, 3, 5

2, 4, 6, 8InputSupply voltage from the carrier board
3.3V-10, 12OutputInternal 3.3V voltage level
3.3VIN13, 15-InputSupply voltage from the carrier board
1.8V39-OutputInternal 1.8V voltage level
JTAG VREF-91OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_64-7, 9InputHigh performance I/O bank voltage
VCCO_65-5InputHigh performance I/O bank voltage
VCCO_669, 11-InputHigh performance I/O bank voltage


Bank Voltages

Bank          

Schematic Name

Voltage

Notes
64 HPVCCO_64UserHP: 1.0V to 1.8V
65 HPVCCO_65UserHP: 1.0V to 1.8V
66 HPVCCO_66UserHP: 1.0V to 1.8V
500 PSMIOVCCO_PSIO0_5001.8V -
501 PSMIOVCCO_PSIO1_5013.3V -
502 PSMIOVCCO_PSIO2_5021.8V-
503 PSCONFIGVCCO_PSIO3_5031.8V-
504 PSDDRVCCO_PSDDR_5041.2V-



Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

DescriptionMinMaxUnitNotes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

PCB thickness: 1.74 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TE0821 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2019-04-26REV01
  • Initial Release
REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.




Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • Initial Release

--

all

  • --


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