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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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Date | Vivado | Project Built | Authors | Description |
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2018-03-29 | 2017.4 | te0710-test_board-vivado_2017.4-build_07_20180329130739.zip te0710-test_board_noprebuilt-vivado_2017.4-build_07_20180329130757.zip | John Hartfiel |
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Issues | Description | Workaround | To be fixed version |
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--- | --- | - | --- |
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
PetaLinux | 2017.4 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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te0710-02-35-2if | 35_2if | REV02 | 512MB | 32MB | ||
te0710-02-35-2cf | 35_2cf | REV02 | 512MB | 32MB | ||
te0710-02-100-2if | 100_2if | REV02 | 512MB | 32MB | ||
te0710-02-100-2cf | 100_2cf | REV02 | 512MB | 32MB |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0701 | |
TE0703 | used as reference carrier |
TE0705 | |
TE0706 | |
TEBA0841 |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
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BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:Xilinx Development Tools
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used on this Example.
Not used on this Example.
Boot process takes a while, please wait.
Note: Linux boot process is slower on Microblaze.
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
set_property PACKAGE_PIN G3 [get_ports {LED_RED_XA_SC[0]}] set_property IOSTANDARD LVCMOS15 [get_ports {LED_RED_XA_SC[0]}] set_property PACKAGE_PIN T10 [get_ports {ETH2_LINK_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_LINK_LED[0]}] set_property PACKAGE_PIN V15 [get_ports {ETH1_LINK_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_LINK_LED[0]}] set_property PACKAGE_PIN T18 [get_ports {ETH1_PD_N[0]}] set_property PACKAGE_PIN D10 [get_ports {ETH2_PD_N[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_PD_N[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_PD_N[0]}] set_property PACKAGE_PIN L15 [get_ports {LED_RED_D3[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_RED_D3[0]}] |
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For SDK project creation, follow instructions from:
Add some Console outputs and changed Bootloader Read Address.
Template location: \sw_lib\sw_apps\srec_spi_bootloader
Changed default Flash Typ to 5.
Template location: \sw_lib\sw_services
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs
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Description currently not available.
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #undef CONFIG_PHY_XILINX #undef XILINX_EMACLITE_BASEADDR 0x40E00000 #undef CONFIG_MII #undef CONFIG_PHY_GIGE #undef CONFIG_PHY_MARVELL #undef CONFIG_PHY_NATSEMI #undef CONFIG_NET_MULTI #undef CONFIG_BOOTP_MAY_FAIL #undef CONFIG_NETCONSOLE 1 #undef CONFIG_SERVERIP 192.168.150.117 #undef CONFIG_IPADDR /* PREBOOT */ #define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo; " |
/include/ "system-conf.dtsi" / { }; /* ETH PHY */ &axi_ethernetlite_0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; }; |
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2018-03-29 | v.1 |
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