Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
TEBF0808
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2020-05-08 | 2019.2 | TE0803-SK_DEMO1_noprebuilt-vivado_2019.2-build_11_20200508143345.zip | Mohsen Chamanbaz |
|
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Software | Version | Note |
---|---|---|
Vitis | 2019.2 | needed, Vivado is included into Vitis installation |
PetaLinux | 2019.2 | needed |
SD Card Formatter | format SD Card | |
Win32 DiskImager | burn generated image on SD | |
SI ClockBuilder Pro | ---- | optional |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|
es1_2gb | REV01 | 2GB | 64MB | NA | NA | Not longer supported by vivado | |
TE0803-01-02EG-1E | 2eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-02CG-1E | 2cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-03EG-1E | 3eg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-03CG-1E | 3cg_2gb | REV01 | 2GB | 64MB | NA | NA | NA |
TE0803-01-02EG-1EA | 2eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-02CG-1EA | 2cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-03EG-1EA | 3eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-03CG-1EA | 3cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-02-03EG-1EB | 3eg_4gb | REV02|REV01 | 4GB | 128MB | NA | NA | NA |
TE0803-01-04CG-1EA | 4cg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04EV-1EA | 4ev_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04EV-1E3 | 4ev_2gb | REV01 | 2GB | 128MB | NA | 1 mm connectors | NA |
TE0803-01-04EG-1EA | 4eg_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-04CG-1EB | 4cg_2gb | REV01 | 2GB | 256MB | NA | NA | NA |
TE0803-01-05EV-1EA | 5ev_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-01-05EV-1IA | 5ev_i_2gb | REV01 | 2GB | 128MB | NA | NA | NA |
TE0803-02-04EV-1EB | 4ev_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0803-02-04EV-1E3 | 4ev_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-02-04EG-1E3 | 4eg_4gb | REV02 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-2AE11-A | 2cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-2BE11-A | 2eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3AE11-A | 3cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-3BE11-A | 3eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4AE11-A | 4cg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4BE11-A | 4eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4BE21-L | 4eg_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4BI21-A | 4eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-4DE11-A | 4ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4DE21-L | 4ev_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4GE21-L | 4eg_2_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-5DE11-A | 5ev_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-5DI21-A | 5ev_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-3RI21-A | 3eg_li_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-3BI21-A | 3eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-4DI21-L | 4ev_i_4gb | REV03 | 4GB | 128MB | NA | 1 mm connectors | NA |
TE0803-03-4GI11-A | 4eg_2i_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4GE11-A | 4eg_2_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-4GI21-A | 4eg_2i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-5BE11-A | 5eg_2gb | REV03 | 2GB | 128MB | NA | NA | NA |
TE0803-03-5DI24-A | 5ev_i_4gb | REV03 | 4GB | 512MB | NA | NA | NA |
TE0803-03-4BI21-X | 4eg_i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0803-03-3BE21-A | 3eg_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0803-03-3AE10-A | 3cg_0_2gb | REV03 | 2GB | NA | NA | NA | NA |
TE0803-03-3AE10-A | 3cg_0_2gb | REV03 | 2GB | NA | NA | NA | NA |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TEBF0808 | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
Cooler | It's recommended to use cooler on ZynqMP device |
USB Cable | Connect to USB2 or better USB3 Hub for proper power supply over USB |
DP Monitor | Optional HW Not all monitors are supported, also Adapter to other Standard can make drouble. Design was testet with DELL U2412M |
Micro USB to USB A Adapter | Adapter for USB Hub |
USB HUB | To connnect Mouse and Keyboard simultaneously |
USB Keyboard | need for Ubuntu/Debian GUI |
USB Mouse | need for Ubuntu/Debian GUI |
DP Cable | -- |
Sata Disk | Optional HW |
SATA Cable | Optional HW |
PCIe Card | Optional HW |
ETH Cable | Optional HW |
SD Card | 16GB |
For general structure and of the reference design, see Project Delivery - AMD devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
---|---|---|
SI5338 | <design name>/misc/Si5338 | SI5338 Project with current PLL Configuration |
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Debian SD-Image | *.img | Debian Image for SD-Card |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Image | --- | Generic Linux kernel binary image file |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Device Tree Blob File | *.dtb | Contains a Device Tree Blob |
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used in this example.
Not used on this Example.
Hard Disk (optional)
To locate root file system on Hard disk:
Activated interfaces:
Type | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
I2C0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 | |
TTC0..3 | |
GEM3 | MIO |
USB0 | MIO/GTP |
SATA | GTP |
DisplayPort | EMIO/GTP |
PCIe | MIO/GTP |
CAN0 | EMIO |
PJTAG0 | MIO |
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
# system controller ip #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B26_L11_P #CAN TX SC18 J3:50 B26_L11_N #CAN S SC16 J3:46 B26_L1_N set_property PACKAGE_PIN G14 [get_ports BASE_sc0] set_property PACKAGE_PIN D15 [get_ports BASE_sc5] set_property PACKAGE_PIN H13 [get_ports BASE_sc6] set_property PACKAGE_PIN H14 [get_ports BASE_sc7] set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B13 [get_ports BASE_sc11] set_property PACKAGE_PIN A14 [get_ports BASE_sc12] set_property PACKAGE_PIN B14 [get_ports BASE_sc13] set_property PACKAGE_PIN F13 [get_ports BASE_sc14] set_property PACKAGE_PIN G13 [get_ports BASE_sc15] set_property PACKAGE_PIN A15 [get_ports BASE_sc16] set_property PACKAGE_PIN B15 [get_ports BASE_sc17] set_property PACKAGE_PIN J14 [get_ports BASE_sc18] set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # Audio Codec #LRCLK J3:49 #BCLK J3:51 #DAC_SDATA J3:53 #ADC_SDATA J3:55 set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ] set_property PACKAGE_PIN L14 [get_ports I2S_bclk ] set_property PACKAGE_PIN E15 [get_ports I2S_sdin ] set_property PACKAGE_PIN F15 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]
For SDK project creation, follow instructions from:
Template location: ./sw_lib/sw_apps/
TE modified 2019.2 FSBL
General:
Module Specific:
TE modified 2019.2 FSBL
General:
Xilinx default PMU firmware.
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card
Changes:
# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="Image"
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"; /* notes: root=/dev/mmcblk1p2 for SD and root=/dev/sda for hard disk will be changed automatically by executing debian/ubuntu script*/ }; }; /* notes: serdes: // PHY TYP see: dt-bindings/phy/phy.h */ /* default */ /* SD */ &sdhci1 { disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 {// SFP2 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // TEBF0808 EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; i2c@6 { // TEBF0808 FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // TEBF0808 Firefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 CPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; };
Start with petalinux-config -c kernel
Changes:
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
File System will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
No additional software is needed.
File location <design name>/misc/Si5338/Si5338-*.slabtimeproj
General documentation how you work with these project will be available on Si5338
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
---|---|---|---|
| |||
-- | all | -- |
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