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Overview
The Trenz Electronic TE0817 is an industrial grade MPSoC SOM integrating a Xilinx Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.
Refer to http://trenz.org/te0817-info for the current online version of this manual and other available documentation.
Key Features
- SoC
- Device: ZU4 / ZU5 / ZU7 1)
- Engine: CG / EG / EV 1)
- Speedgrade: -1 / -2 / -3 1)
- Temperature Range: Extended / Industrial 1)
- Package: FBVB900
- RAM/Storage
- 4 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- EEPROM with MAC address
- On Board
- Oscillator
- Interface
- 4 x B2B Connector (ADM6)
up to 204 PL IO
- HP: 156
- HD: 48
up to 65 PS MIO
- 4 GTR
- 16 GTH
- I2C, JTAG
- 4 x B2B Connector (ADM6)
- Power
- 3.3 V power supply via B2B Connector needed 4).
- Dimension
- 76 mm x 52 mm
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
2) Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s.
3) Please, take care of the possible assembly options.
4) Dependant on the assembly option a higher input voltage may be possible.
Block Diagram
Main Components
- SoC, U1
- DDR4, U2, U3, U9, U12
- Quad SPI Flash, U7, U17
- Connector, J1, J2, J3, J4
- EEPROM, U11
- Clock Generator, U5
- Oscillator, U25, U32
- Power Supply, U4, U6, U8, U10, U13 ... U15, U18 ... U24, U26 ... U31, U34, U38
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
DDR4 SDRAM | not programmed | |
Quad SPI Flash | not programmed | |
EEPROM | not programmed besides factory programmed MAC address | |
Programmable Clock Generator | not programmed |
Signals, Interfaces and Pins
Connectors
Connector Type | Designator | Interface | IO CNT 1) | Notes |
---|---|---|---|---|
B2B | JM1 | MGT PL | 12 x MGT (RX/TX) | |
B2B | JM1 | HP | 52 SE / 24 DIFF | |
B2B | JM2 | MGT PS | 2 x MGT CLK | |
B2B | JM2 | CLK | DIFF CLK | |
B2B | JM2 | MGT PL | 4 x MGT (RX/TX) | |
B2B | JM2 | MGT PS | 4 x MGT (RX/TX) | |
B2B | JM2 | CFG | JTAG | |
B2B | JM2 | CFG | MODE | |
B2B | JM3 | HD | 48 SE / 24 DIFF | |
B2B | JM3 | MGT PL | 3 x MGT CLK | |
B2B | JM3 | CLK | DIFF CLK | |
B2B | JM3 | MIO | 65 GPIO | |
B2B | JM4 | HP | 104 SE / 48 DIFF |
1) IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs
Test Points
Test Point | Signal | Notes1) |
---|---|---|
TP1 | PLL_SCL | pulled-up to SI_PLL_1V8 |
TP2 | PLL_SDA | pulled-up to SI_PLL_1V8 |
TP5 | GND | |
TP6 | TCK | |
TP7 | TDI | |
TP8 | TDO | |
TP9 | TMS | |
TP12 | PL_VCCINT | |
TP15 | FP_0V85 | |
TP16 | DDR_2V5 | |
TP17 | DCDC_2V0 | |
TP18 | DDR_PLL | |
TP20 | PL_VCU | |
TP23 | VTT | |
TP24 | AUX_R | |
TP25 | AVTT_R | |
TP26 | AVCC_R | |
TP27 | PS_PLL | |
TP28 | PS_AVTT | |
TP29 | PS_AUX | |
TP30 | PS_AVCC | |
TP31 | LP_0V85 | |
TP32 | GND |
1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
On-board Peripherals
Chip/Interface | Designator | Connected To | Notes |
---|---|---|---|
DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS | |
Quad SPI Flash | U7, U17 | SoC - PS | Booting. |
EEPROM | U11 | B2B - J2 | |
Clock Generator | U5 | SoC, B2B | |
Oscillator | U25 | Clock Generator | 25 MHz |
Oscillator | U32 | SoC | 33.333333 MHz |
Configuration and System Control Signals
Connector+Pin | Signal Name | Direction1) | Description |
---|---|---|---|
JM1.A45 | POR_OVERRIDE | IN | Override power-on reset delay 2). |
JM2.A30 | PG_PLL_1V8 | OUT | SI_PLL_1V8 power rail powered-up. |
JM2.A31 | ERR_OUT | OUT | PS error indication 2). |
JM2.A34 | ERR_STATUS | OUT | PS error status 2). |
JM2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN |
JM2.A36 | PLL_SCL | IN | I2C clock |
JM2.A37 | PLL_SDA | IN/OUT | I2C data |
JM2.A40 | PG_VCU | OUT | VCU power rail powered-up. |
JM2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. |
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 |
JM2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. |
JM2.B30 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. |
JM2.B33 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. |
JM2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR 2). Pulled-up to PS_1V8. |
JM2.B37 | PG_PL | OUT | Programmable logic powered-up. |
JM2.B38 | EN_FPD | IN | Enable full-power domain power-up. |
JM2.B41 | PG_FPD | OUT | Full-power domain powered-up. |
JM2.B42 | EN_LPD | IN | Enable low-power domain power-up. |
JM2.B45 | PG_DDR | OUT | DDR power supply powered-up. |
JM2.B46 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. |
JM2.B47 | EN_DDR | IN | Enable DDR power-up. |
JM2.C30 | EN_GT_L | IN | Not connected. |
JM2.C31 | MR | IN | Manual reset. |
JM2.C32 | PLL_SEL0 | IN | PLL clock selection. |
JM2.C33 | PLL_RST | IN | PLL reset. |
JM2.C35 | EN_PL | IN | Enable programable logic power-up. |
JM2.C36 | EN_GT_R | IN | Enable GTH transceiver power-up. |
JM2.C37 | PLL_FDEC | IN | PLL Frequency decrementation. |
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47 | MODE3..0 | IN | Boot mode selection 2):
Supported Modes depends also on used Carrier. |
JM2.D29 | EN_PLL_PWR | IN | Enable PLL power supply. |
JM2.D30 | PLL_FINC | IN | PLL Frequency incrementation. |
JM2.D31 | PLL_LOLn | OUT | Loss of lock status. |
JM2.D32 | PLL_SEL1 | IN | PLL clock selection. |
JM2.D33 | PG_GT_R | OUT | GTH Transceivers powered-up. |
JM2.D37 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). |
JM2.D38 | PUDC_B | IN | Configuration pull-ups setting 2). Pulled-up to PL_1V8. |
JM2.D45 / JM2.D46 | DX_P / DX_N | - | SoC temperatur sensing diode pins 2). |
1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) See UG1085 for additional information.
3) See Recommended Operating Conditions.
Power and Power-On Sequence
Power Rails
Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
---|---|---|---|
VCCO_66 | JM1.A32 / JM1.A33 | IN | |
VREF_66 | JM1.A41 | IN | |
3.3VIN | JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56 | IN | |
PL_1V8 | JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34 | OUT | |
PL_DCIN | JM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 | IN | |
LP_DCDC | JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52 | IN | |
DCDCIN | JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / | IN | |
PS_BATT | JM2.D37 | IN | |
DDR_1V2 | JM2.D47 | OUT | |
PS_1V8 | JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56 | OUT | |
PLL_3V3 | JM3.A55 | IN | |
GT_DCDC | JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 / | IN | |
VCCO_48 | JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9 | IN | |
VCCO_47 | JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21 | IN | |
VCCO_64 | JM4.B21 / JM4.B39 | IN | |
VREF_64 | JM4.B30 | IN | |
VCCO_65 | JM4.C21 / JM4.C39 | IN | |
VREF_65 | JM4.C30 | IN |
1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
Recommended Power up Sequencing
The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
---|---|---|---|---|---|
0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. |
1 | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. |
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.): | |||||
1 1) | GT_DCDC | 3.3 V (± 5 %) 2) | GTH transceiver power supply. | Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. | |
1 1) | EN_PLL_PWR | - | PD 3), GND | PLL power enable. | |
1 1) | PG_PLL_1V8 | - | PU 3), 3.3 V | PLL power good status. | |
2 | Processing System (PS): | Procedure for PS starting. | |||
2.1 | Low-power domain: | Bring-up for low-power domain PS. | |||
2.1.1 | LP_DCDC | 3.3 V (± 5 %) 2) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
2.1.2 | EN_LPD | - | PU 3), 3.3 V | Low-power domain power enable. | |
2.1.3 | LP_GOOD | - | PU 3), 3.3 V | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. |
2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. | ||
2.2.1 | DCDCIN | 3.3 V (± 5 %) 2) | Full-power domainand GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. | |
2.2.2 | EN_FPD | 3.3 V | - | Full-power domain power enable. | |
2.2.3 | PG_FPD | - | PU 3), 3.3 V | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. |
2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. | |
2.2.5 | PG_DDR | PU 3), 3.3 V | DDR memory power good status. | Module power-on sequencing for DDR memory finished. | |
2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). | ||
2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. | |
2.3.2 | PG_PSGT | - | PU 3), 3.3 V | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. |
2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. | ||
2.1 | PL_DCIN | 3.3 V (± 5 %) 2) 4) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. |
2.2 | EN_PL | - | PU 3), 3.3 V | Programmable logic power enable. | |
2.3 | PG_PL | - | PU 3), 3.3 V | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. |
2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 5) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. |
2.5 | PG_VCU | - | PU 3), 3.3 V | VCU power good status. | |
3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. | ||
3.1 | GT_DCDC | 3.3 V (± 5 %) 2) | - | GTH transceiver power supply. | Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. |
3.2 | EN_GT_R | 3.3 V | - | GTH / GTY transceiver power enable. | |
3.3 | PG_GT_R | - | PU 3), 3.3 V | GTH / GTY transceiver power good status. |
1) (optional)
2) Dependent on the assembly option a higher input voltage may be possible.
3) (on module)
4) This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.
5) See DS925 for additional information.
Board to Board Connectors
- 4x ADM6-60-01.5-L-4-2 (240 pins, 60 per row)
- Mates with ADF6-60-03.5-L-4-2
5.2 x 7.6 cm UltraSoM+ carrier use four Samtec AcceleRate HD High-Density Slim Body Arrays on top side.
- 4x ADF6-60-03.5-L-4-2 (160-pins)
- Mates with ADM6-60-01.5-L-4-2
Features
- Board-to-Board Connector 240-pins, 60 contacts per row
- 0.025" (0.635 mm) pitch
- Data Rate: max 56 Gbps
- Mates with: ADM6/APF6
- Insulator Material: LCP, Black
- Contact Material: Copper Alloy
- Plating: Au or Sn over 50 µ" (1.27 µm) N
- Operating Temperature Range: -55 ºC to +125 ºC
- PCIe 5.0 capable: Yes
- Lead-Free Solderable: Yes
- RoHS Compliant: Yes
Connector Stacking height
When using the standard type on baseboard and module, the mating height is 5 mm.
Other mating heights are possible by using connectors with a different height:
Order number | REF number | Samtec Number | Type | Contribution to stacking height | Comment |
---|---|---|---|---|---|
30095 | REF-30095 | ADM6-60-01.5-L-4-2 | Module connector | 1.5 mm | Standard connector used on modules |
31137 | REF-31137 | ADF6-60-03.5-L-4-2 | Baseboard connector | 3.5 mm | Standard connector used on carrier |
Connector Speed Ratings
The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:
Stacking height | Speed rating |
---|---|
5 mm | 56 Gbps |
Current Rating
Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered)
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
Manufacturer Documentation
File | Modified | |
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PDF File 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adf6.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File ADF6-XXX-XX.X-XXX-X-X-X-FOOTPRINT.PDF | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adf6-xxx-xx.x-xxx-x-x-x-xr-mkt.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adx6 mated document.pdf | 10 01, 2022 by Martin Rohrmüller | |
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Technical Specifications
Absolute Maximum Ratings *)
Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
---|---|---|---|---|
LP_DCDC | Micromodule Power | -0.300 | 6.0 | V |
DCDCIN | Micromodule Power | -0.300 | 7.0 | V |
GT_DCDC | Micromodule Power | -0.300 | 6.0 | V |
PL_DCIN 1) | Micromodule Power | -0.300 | 4.0 | V |
3.3VIN | Micromodule Power | -0.300 | 3.600 | V |
PLL_3V3 | PLL power supply | -0.500 | 3.8 | V |
PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V |
VCCO_47 | HD IO Bank power supply | -0.500 | 2.000 | V |
VCCO_48 | HD IO Bank power supply | -0.500 | 2.000 | V |
VCCO_64 | HP IO Bank power supply | -0.500 | 3.400 | V |
VCCO_65 | HP IO Bank power supply | -0.500 | 3.400 | V |
VCCO_66 | HP IO Bank power supply | -0.500 | 3.400 | V |
VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
1) This value depends highly on DCDC U4. Higher values are possible with different DCDCs. For more information consult schematic and according datasheets.
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be different depending on assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
LP_DCDC 1) | 3.135 | 3.465 | V | |
DCDCIN 1) | 3.135 | 3.465 | V | |
GT_DCDC 1) | 3.135 | 3.465 | V | |
PL_DCIN 1) 2) | 3.135 | 3.465 | V | |
3.3VIN | 3.135 | 3.465 | V | |
PLL_3V3 | 3.135 | 3.465 | V | |
PS_BATT | 1.2 | 1.5 | V | See FPGA datasheet. |
VCCO_47 | 1.164 | 3.399 | V | See FPGA datasheet. |
VCCO_48 | 1.164 | 3.399 | V | See FPGA datasheet. |
VCCO_64 | 0.97 | 1.854 | V | See FPGA datasheet. |
VCCO_65 | 0.97 | 1.854 | V | See FPGA datasheet. |
VCCO_66 | 0.97 | 1.854 | V | See FPGA datasheet. |
VREF_64 | 0.6 | 1.2 | V | See FPGA datasheet. |
VREF_65 | 0.6 | 1.2 | V | See FPGA datasheet. |
VREF_66 | 0.6 | 1.2 | V | See FPGA datasheet. |
1) Dependent on the assembly option a higher input voltage may be possible.
2) This value depends highly on DCDC U4. Higher values may possible with different DCDCs. For more information consult schematic and according datasheets.
Physical Dimensions
Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
PCB thickness: 1.74 mm (± 10 %) (???).
Currently Offered Variants
Trenz shop TE0817 overview page | |
---|---|
English page | German page |
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
---|---|---|---|
- | REV01 | First Production Release | REV01 |
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributor | Description |
---|---|---|---|
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Disclaimer
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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Copyright Notice
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Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
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REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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