Overview

This tutorial [1] describes configuration of an extensible platform for TE0950 board [6], [7], [8] and compilation of PetaLinux 2023.2 system on TE0950-02 (ES1 device) or TE0950-03 (production device) board for Vivado/Vitis 2023.2.1 toolchain.

This tutorial [1] is base for the TE0950 tutorials:

TE0950 Integration of DPUCZDX8G [2]
TE0950 Integration of DPUCV2DX8G [3]
TE0950 AI 3.0 Models for DPUCZDX8G [4]
TE0950 AI 3.5 Models for DPUCV2DX8G [5]

The TE0950 extensible bring up script are using Linux make utility. 
The board configuration files are identical with [6], [7] for the Versal device.
The Artix device is using the bring up scripts and board configuration files [6], [8].

Requirements

Download package TE0950_2023_2_1_extensible.zip accompanying this tutorial from:

https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Development_Boards/TE0950/Reference_Design/2023.2/VitisAI/TE0950_2023_2_1_extensible.zip

It contains files for the directory: 
dpucv2dx8g-trd\te0950_platform.

Change console from dash to bash

sudo dpkg-reconfigure dash 

Press No to disable dash and activate default bash

Enable i386 architecture

sudo dpkg --add-architecture i386
sudo apt-get update

Install packages

sudo apt-get install iproute2 gawk python3 build-essential gcc git make net-tools libncurses5-dev tftpd zlib1g-dev libssl-dev flex bison libselinux1 gnupg wget git diffstat chrpath socat xterm autoconf libtool tar unzip texinfo zlib1g-dev gcc-multilib automake zlib1g:i386 screen pax gzip cpio python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint bc libtinfo5 subversion u-boot-tools -y

Installation of Vitis and Vivado 2023.2

Extract installation files from the archive downloaded from the AMD Vitis Core Development Kit - 2023.2 Full Project installation: 

tar -xvf FPGAs_AdaptiveSoCs_Unified_2023.2_1013_2256.tar.gz

 Create Folder /tools/Xilinx 

sudo mkdir /tools
sudo mkdir /tools/Xilinx

 Change <owner> to user name 

sudo chown <owner>:<owner> /tools/Xilinx

 Example: for user devel 

sudo chown devel:devel /tools/Xilinx

 Install Vitis 2023.2 by: 

$ ./xsetup

 Install additional libraries by executing: 

/tools/Xilinx/Vitis/2023.2/scripts/installLibs.sh

Installation of Petalinux 2023.2

Install Petalinux 2023.2 from the same archive downloaded from the AMD Vitis Core Development Kit - 2023.2 Full Project installation:

$ ./xsetup

Installation of Vivado 2023.2.1

An additional upgrade of Vivado 2023.2 to Vivado 2023.2.1 is needed to for the XCVE2302 device.

Extract installation files from the downloaded archive or use the included untared set: 

tar -xvf Vivado_Vitis_Update_2023.2.1_1214_1912.tar.gz

 Install Vitis 2023.2.1 by: 

$ ./xsetup

Installation of csh

Compilation process for creation of the AI-ML DPU engine contains scripts which will require the csh shell. It is not included in the Ubuntu 20.4 LTE by default. Install csh by: 

sudo apt install csh 

Rename 

Compilation process for creation of the AI-ML engine will require command rename. It is not included in Ubuntu 20.4 LTE by default. Install rename by: 

sudo apt install rename

Copy dpucv2dx8g-trd.zip archive accompanying this application note to

~/Downloads/dpucv2dx8g-trd.zip

Unzip the file to the directory:

~/work/dpucv2dx8g-trd

HDMI display

By default, the HDMI display is disabled by selection HDMI_EN = 0 in file dpucv2dx8g-trd\te0950_platform\user_config.mk .

If the HDMI display is enabled by selection HDMI_EN = 1, the licenses for at least evaluation version of v_hdmi and v_hdmi1 IPs are needed.

Additional installations required only for the TE0950-02 board

Compilation for the TE0950-02 board with XCVE2302-ES1 device requires additional license enablement for ES devices. Contact your local AMD representative.

The license will have to be generated by AMD account name:

VERSAL AI Edge PDI Early Access

It contains Certificate-Full enablement features for Versal AI Edge devices. This includes the xcve2302-es1 device used on the TE0950-02 board:

xcve2302-es1
xcve2302-es1_bitgen

In AMD licensing portal, use the VERSAL AI Edge PDI Early Access account for generation of license file for your PC with these two features.

Append the generated license file to your license file. The AMD Vivado 2023.2.1 toolchain is enabled for synthesis, simulation and for generation of bitstreams for the AMD Versal AI Edge ES1 devices.

Vivado and Vitis HLS tools require creaton of two additional initialisation scripts. These scripts enable the initial search the AMD Versal AI Edge ES1 device files.

Create file to enable ES devices in Vivado: 

/tools/Xilinx/Vivado/2023.2/scripts/Vivado_init.tcl

 Write to this file this single line command:

enable_beta_device xcve*

Create file to enable ES devices in Vitis HLS:

/tools/Xilinx/Vitis_HLS/2023.2/scripts/HLS_init.tcl

Write to this file this single line command:

enable_beta_device xcve*

Aditional modifications of installation package for the TE0950-02 ES1 device.

Installation package for the TE0950-02 with XCVE2302-ES1 device requires these three changes for compilation of HW platform for ES1 device:

1: te0950_platform\hw\tcl\001-create_proj.tcl 

15 # Create project
16 create_project ${proj_name} . -part xcve2302-sfva784-1LP-e-S
17 set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.1    [current_project]

 To

15 # Create project
16 create_project ${proj_name} . -part xcve2302-sfva784-1LP-e-S-es1
17 set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.0    [current_project]

2: te0950_platform\hw\tcl\main.tcl

37 # Create project
38 create_project -name ${proj_name} -force -dir . -part xcve2302-sfva784-1LP-e-S
39 set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.1 [current_project]15

To

37 # Create project
38 create_project -name ${proj_name} -force -dir . -part xcve2302-sfva784-1LP-e-S-es1
39 set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.0 [current_project]

3: te0950_platform\hw\tcl\vu_sys.tcl

74 set list_projs [get_projects -quiet]
75 if { $list_projs eq "" } {
76   create_project project_1 myproj -part xcve2302-sfva784-1LP-e-S
77   set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.1 
   [current_project]
78 }

To

74 set list_projs [get_projects -quiet]
75 if { $list_projs eq "" } {
76   create_project project_1 myproj -part xcve2302-sfva784-1LP-e-S-es1
77   set_property BOARD_PART trenz.biz:te0950_23_1lse:part0:1.0 
   [current_project]
78 }

Installation package with these changes will create extensible custom platform for the TE0950-02 board with XCVE2302-ES1 device.

Installation package without these changes will create extensible custom platform for the TE0950-03 board with XCVE2302 device.

Next steps are identical for TE0950-02 board with XCVE2302-ES1 device as well a for the

TE0950-03 board with XCVE2302 device.

Extensible Custom Platform for TE0950-03 board

The archave dpucv2dx8g-trd.zip has been allready unzipped to the directory: 

~/work/dpucv2dx8g-trd

Reference HW for TE0950-03 board

In Ubuntu terminal, change directory to:

$ cd ~/work/dpucv2dx8g-trd/te0950_platform

In Ubuntu terminal, source paths to Vitis and Vivado 2023.2.1 tools by

$ source /tools/Xilinx/Vitis/2023.2/settings64.sh

Use make to create TE0950-03 reference platform hardware and export it as an extensible platform archive by command:

$ make –C hw

Cration of platform and export  takes some time and requires sufficient free disk space.

Reference platform is exported as TE0950_VAI.xsa archive: 

~/work/dpucv2dx8g-trd/te0950_platform/hw/build/TE0950_VAI.xsa

Created TE0950_VAI.xsa platform supports extensible flow with 100, 150, 200, 250 and 300 MHz clocks for IP cores in the programmable logic.

In Vivado, open HW design and generate pdf of created block diagram by clicking to any place in diagram window and selecting Save as PDF File. Use the default file name:

~/work/dpucv2dx8g-trd/te0950_platform/hw/build/vu_sys.pdf

Custom platform – top level

Custom platform – platform block

Custom platform – hdmi block

Custom platform – cruvi_1 block

Custom platform – cruvi_2 block

Building Petalinux for Vitis AI 3.5

Vitis AI 3.5 library

Petalinux 2023.2.1 contains recepies for the Vitis-AI 3.5 library.

Building Petalinux for Extensible Design Flow

Change directory to the default Petalinux direktory:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950

Source Vitis and Petalinux scripts to set environment for access to Vitis and PetaLinux tools.

$ source /tools/Xilinx/Vitis/2023.2/settings64.sh
$ source /tools/Xilinx/PetaLinux/2023.2/tool/settings.sh

Configure Petalinux with extensible hw platform defined in the archive

~/work/dpucv2dx8g-trd/te0950_platform/hw/build/TE0950_VAI.xsa

 for the extensible design flow by executing: 

$ petalinux-config --get-hw-description=
/home/<user>/work/dpucv2dx8g-trd/te0950_platform/hw/build

Replace <user> by your user name. 
In our case, <user>=devel we use: 

$ petalinux-config --get-hw-description=
/home/devel/work/dpucv2dx8g-trd/te0950_platform/hw/build

Select Exit->Yes to close this window.

See the user-rootfsconfig file:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/
project-spec/meta-user/conf/user-rootfsconfig

It contains these lines:

#Note: Mention Each package in individual line
#These packages will get added into rootfs menu entry
CONFIG_packagegroup-base-trd
CONFIG_libgpiod-tools
CONFIG_mipi-example
CONFIG_startup
CONFIG_avs-gst-resnet50
CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv
CONFIG_packagegroup-petalinux-opencv-dev
CONFIG_dnf
CONFIG_e2fsprogs-resize2fs
CONFIG_parted
CONFIG_resize-part
CONFIG_packagegroup-petalinux-vitisai
CONFIG_packagegroup-petalinux-self-hosted
CONFIG_cmake
CONFIG_packagegroup-petalinux-vitisai-dev
CONFIG_mesa-megadriver
CONFIG_packagegroup-petalinux-x11
CONFIG_packagegroup-petalinux-v4lutils
CONFIG_packagegroup-petalinux-matchbox
CONFIG_packagegroup-petalinux-vitis-acceleration
CONFIG_packagegroup-petalinux-vitis-acceleration-dev
CONFIG_packagegroup-petalinux-vitis-acceleration-essential
CONFIG_packagegroup-petalinux-vitis-acceleration-essential-dbg
CONFIG_packagegroup-petalinux-vitis-acceleration-essential-dev
CONFIG_packagegroup-core-ssh-dropbear
CONFIG_imagefeature-ssh-server-dropbear
CONFIG_imagefeature-ssh-server-openssh
CONFIG_openssh
CONFIG_openssh-sftp-server
CONFIG_openssh-sshd
CONFIG_openssh-scp
CONFIG_imagefeature-package-management
CONFIG_imagefeature-debug-tweaks

xrt, xrt-dev and zocl  are required for Vitis acceleration flow.
dnf is for package management.
parted, e2fsprogs-resize2fs and resize-part can be used for ext4 partition resize.

Other included packages serve for natively building Vitis AI applications on target board and for running Vitis-AI demo applications with GUI.

The Vitis-AI 3.5 recepies for installation of the correspoding Vitis-AI 3.5 libraries into rootfs of PetaLinux are specified allready as selected recepies in PetaLinux 2023.2

Launch rootfs config:

$ petalinux-config -c rootfs

Enable user packages

Select user packages

[*] libgpiod-tools
[*] avs-gst-resnet50
[*] cmake
[*] dnf
[*] e2fsprogs-resize2fs
[*] imagefeature-debug-tweaks
[*] imagefeature-package-management
[ ] imagefeature-ssh-server-dropbear
[*] imagefeature-ssh-server-openssh
[*] mesa-megadriver
[*] mipi-example
[*] opencl-clhpp-dev
[*] opencl-headers-dev
[*] openssh
[*] openssh-scp
[*] openssh-sftp-server
[*] openssh-sshd
[ ] packagegroup-base-trd
[ ] packagegroup-core-ssh-dropbear
[*] packagegroup-petalinux-matchbox
[*] packagegroup-petalinux-opencv
[*] packagegroup-petalinux-opencv-dev
[*] packagegroup-petalinux-self-hosted
[*] packagegroup-petalinux-v4lutils
[*] packagegroup-petalinux-vitis-acceleration
[*] packagegroup-petalinux-vitis-acceleration-dev
[*] packagegroup-petalinux-vitis-acceleration-essential
[ ] packagegroup-petalinux-vitis-acceleration-essential-dbg
[*] packagegroup-petalinux-vitis-acceleration-essential-dev
[*] packagegroup-petalinux-vitisai
[*] packagegroup-petalinux-vitisai-dev
[*] packagegroup-petalinux-x11
[*] parted
[*] resize-part
[*] startup
[*] xrt
[*] xrt-dev
[*] zocl

Select packages as indicated by [*]

Still in the RootFS configuration window, go to root directory. Select Exit and Yes to Save changes.

Disable CPU IDLE in Kernel Config

CPU IDLE would cause processors get into IDLE state (WFI) when the processor is not in use. When JTAG is connected, the hardware server on host machine talks to the processor regularly. If it talks to a processor in IDLE status, the system will hang because of incomplete AXI transactions.

So, it is recommended to disable the CPU IDLE feature during project development phase.

It can be re-enabled after the design has completed to save power in final products.

Launch kernel config:

$ petalinux-config -c kernel

Ensure the following items are TURNED OFF in both menu selections:

CPU Power Management->CPU Idle->CPU idle PM support
CPU Power Management->CPU Frequency scaling->CPU Frequency scaling

Select Exit and Yes to Save changes.

Add EXT4 rootfs Support

Let PetaLinux generate EXT4 rootfs. In terminal, execute:

$ petalinux-config

Go to Image Packaging Configuration.
Enter into Root File System Type

Select Root File System Type  EXT4

Change the Device node of SD device from the default value

/dev/mmcblk0p2

to new value required for the TE0950-03 board:

/dev/mmcblk1p2

Go to

Image Packaging Configuration

modify Root filesystem formats from

cpio cpio.gz cpio.gz.u-boot ext4 tar.gz jffs2

to

ext4

Select Exit and Yes to save changes.

Let PetaLinux Use EXT4 rootfs During Boot

The setting of which rootfs to use during boot is controlled by bootargs. We would change bootargs settings to allow Linux to boot from EXT4 partition.

In terminal, execute:

$ petalinux-config

Change DTG settings->Kernel Bootargs->generate boot args automatically to NO.

Update User Set Kernel Bootargs to:

console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait cma=512M

Click OK, Exit three times and Save.

Build PetaLinux Image

In terminal, build the PetaLinux project by executing:

$ petalinux-build

The PetaLinux image files will be generated in the directory:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux

Generation of PetaLinux takes some time and requires Ethernet connection and sufficient free disk space.

Create PetaLinux SDK

The SDK will be used by Vitis tool to cross compile applications for newly created platfom.

In terminal, execute:

$ petalinux-build --sdk

The generated sysroot package sdk.sh will be located in directory

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux

Generation of SDK package takes some time and requires sufficient free disk space.
Time needed for these two steps depends also on number of allocated processor cores.

Copy Files for Extensible Platform

Create new folders for the extensible platform:

~/work/dpucv2dx8g-trd/te0950_pfm/pfm/boot
~/work/dpucv2dx8g-trd/te0950_pfm/pfm/sd_dir

Copy these files: 

 Rename the copied file u-boot-dtb.elf  to u-boot.elf

The directory

~/work/dpucv2dx8g-trd/te0950_pfm/pfm/boot

contains these files:

bl31.elf
plm.elf
psmfw.elf
system.dtb
u-boot.elf

Copy files:

Create Extensible Platform Archive (optional)

Create new directory tree:

~/work/dpucv2dx8g-trd_move/os/petalinux/images
~/work/dpucv2dx8g-trd_move_pfm/pfm/boot 
~/work/dpucv2dx8g-trd_move_pfm/pfm/sd_dir

Copy all files from the directory:

 Zip the directory

~/work/dpucv2dx8g-trd_move

into ZIP archive:

~/work/dpucv2dx8g-trd_move.zip

The archive dpucv2dx8g-trd_move.zip can be used to create extensible platform on the same or on an another PC with installed Ubuntu 20.04 and Vitis tools, with or without installed Petalinux. The archive includes all needed components, and script sdk.sh serving for generation of the sysroot.

Clean PetaLinux Files (optional)

The Petalinux compilation process has created round 50 GBytes of files which can be deleated to save Ubuntu disk space.

Change directory to the default Petalinux folder

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950

Source Vitis and Petalinux scripts to set environment for access to Vitis and PetaLinux tools.

$ source /tools/Xilinx/Vitis/2023.2/settings64.sh
$ source /tools/Xilinx/PetaLinux/2023.2/tool/settings.sh

Clean Petalinux project files by command

$ petalinux-build -x mrproper

This will delete also final files needed PetaLinux files in the images directory.
Restore deleated PetaLinux output files to the images directory.

Back-up dpucv2dx8g-trd_move.zip archive.

Delete: 

~/work/dpucv2dx8g-trd_move
~/work/dpucv2dx8g-trd_move.zip 

Clean the Debian Trash.

Generation of SYSROOT

In Ubuntu terminal, change the working directory to:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux

In Ubuntu terminal, execute script enabling access to Vitis 2023.2 tools.

$ source /tools/Xilinx/Vitis/2023.2/settings64.sh

In Ubuntu terminal, execute script

$ ./sdk.sh -d /home/<user>/work/dpucv2dx8g-trd/te0950_pfm

For <user>= devel

$ ./sdk.sh -d /home/devel/work/dpucv2dx8g-trd/te0950_pfm

Script creates SYSROOT directories and files in:

~/work/dpucv2dx8g-trd/te0950_pfm/sysroots/x86_64-petalinux-linux
~/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux

Once created, do not move these directories (due to internally created absolute paths).

Generation of Extensible Platform for Vitis 2023.2.1

In Ubuntu terminal, change the working directory to:

~/work/dpucv2dx8g-trd/te0950_pfm

Start the vitis --classic version of Vitis tool by executing

$ vitis --classic -workspace . &

Click on “Launch” to launch vitis --classic version of Vitis

Close Welcome page.

In Vitis, select in the main menu: File -> New -> Platform Project

Type name of the extensible platform:  te0950_300_pfm. Click Next.

For hardware specification, select extensible platform archive:

~/work/dpucv2dx8g-trd/te0950_platform/hw/build/TE0950_VAI.xsa

In Software specification select: linux
Modify domain linux_domain by opening text entry editing window related to Description. Write: 

xrt  

In Bif File find and select the pre-defied option:  

Generate Bif

In Boot Components Directory select:

~/work/dpucv2dx8g-trd/te0950_pfm/pfm/boot

In FAT32 Partition Directory select:

~/work/dpucv2dx8g-trd/te0950_pfm/pfm/sd_dir

In Vitis IDE Explorer section, click on te0950_300_pfm to highlight it.

Right-click on the highlighted te0950_300_pfm and select build project in the open submenu. Platform is compiled in few seconds.
Close the Vitis tool by selection: File -> Exit.

Vits extensible platform te0950_300_pfm has been created in the directory:

~/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm

Platform Usage

Read Platform Info

With Vitis environment setup, platforminfo tool can report platform information.

Create, compile and test vector addition example

Create new directory te0950_test_vadd  to test Vitis extendable flow example “vector addition”

~/work/dpucv2dx8g-trd/te0950_test_vadd

Current directory structure:

~/work/dpucv2dx8g-trd/te0950_platform
~/work/dpucv2dx8g-trd/te0950_pfm
~/work/dpucv2dx8g-trd/te0950_test_vadd

Change working directory:

$ cd ~/work/dpucv2dx8g-trd/te0950_test_vadd

In Ubuntu terminal, start vitis --classic verson of Vitis 2023.2.1 by:

$ vitis --classic -workspace . &

Click on Launch to launch Vitis.
Select File -> New -> Application project. Click Next.

Skip welcome page if shown.

Click on [+ Add] icon and select the custom extensible platform in the directory:

~/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm

We can see available PL clocks and frequencies. PL4 with 300 MHz clock was set as default in the platform creation process.

Click Next.
In Application Project Details window type into Application project name: test_vadd
Click Next.
In Domain window  type (or select by browse):

Sysroot path:

~/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux

Root FS:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux
rootfs.ext4

Kernel Image:

~/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux/
Image

Click Next.

In Templates window, if not done before, update Vitis IDE Examples and Vitis IDE Libraries.

Select Host Examples:
In Find, type: vector add to search for the Vector Addition example.

Select: Vector Addition
Click Finish
New project template is created.

In test_vadd window menu “Active build configuration” switch from SW Emulation to Hardware.

In Explorer section of Vitis -classic IDE, click on:  test_vadd_system to select it.

Right Click on:  test_vadd_system and select in the opened sub-menu: Build project

Vitis will compile HW and SW. This step can take some time.

Created system with integrated vadd HW IP block can be open and analysed in Vivado 2023.2.1.

test_vadd top

Test_vadd vitis_region

 Generated connections of platform with Vitis region. Clock 300 MHz is highlighted.

Run test_vadd

The sd_card.img file is output of the compilation and packing made by Vitis 2023.2.1. Image  is located:

~/work/dpucv2dx8g-trd/te0950_test_vadd/test_vadd_system/
Hardware/package/sd_card.img

Write the sd card image sd_card.img to the SD card. Application Win32DiskImager can be used for this task in Windows Pro 10 (or Windows 11 Pro) PC. It can be downloaded from

https://win32diskimager.org/

• Insert the SD card to the board.
• Connect PC USB terminal (115200 bps) to the board.
• Connect Ethernet cable to the board.
• Power on the board.
• In PC, find the assigned serial line COM port number for the USB terminal.
  In case of Win 10 Pro or Win 11 Pro, use Device manager to find it.
• In PC, open serial line terminal with the assigned COM port number. Speed 115200 bps.
• In PC terminal, type:

sh-5.0# cd /run/media/mmcblk1p1/
sh-5.0# ./test_vadd binary_container_1.xclbin

The application test_vadd should run with this output:

INFO: Reading binary_container_1.xclbin
Loading: ' binary_container_1.xclbin '
Trying to program device[0]: edge
Device[0]: program successful!
TEST PASSED

• To halt Linux system, type in the USB terminal:

# halt

• Petalinux system is halted and all file system related caches are closed.
• Messages related to halt of the system can be seen on the USB terminal.
• The SD card can be safely removed from the TE0950-03 board in halt state.
• The terminal can be closed and USB terminal cable can be disconnected.
• Board can be disconnected from power.

Integration of AIE-ML engine

This section demonstrates how to compile algorithm running on AI-ML engine, how to  integrate it on the te0950_300_pfm, how to execute it on TE0950-03 board with Petalinux OS and verrify correct results.
The example of AIE-ML Engine domain application contains a simple graph consisting of three kernels. These kernels are connected by both windows and streams. 
The PL domain contains data movers that provide input and capture output from the AI Engine. 
The PS domain contains a host application that controls the entire system. The SW application is using XRT API and runs on PetaLinux. 
Design running on these heterogeneous domains is validated by running on actual hardware. SW application compare results with the golden reference computed by the PS SW.
This system integration example for the TE0950-03 board is based on the example for the AMD VEK280 development kit published by AMD in this section of the 2023.2 tutorials:

AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration

It integrates these kernels and AIE-ML programs:

MM2S is a HLS kernel. It performs Memory Map to Stream HLS kernel to feed input data from DDR to AIE-ML Engine interpolator kernel via the PL DMA.

Interpolator  is an AIE-ML program. It performs Half-band 2x up-sampling FIR filter with 16 coefficients. Its input and output are cint16 window interfaces and the input interface has a 16 sample margin.

Polar_clip is an AIE-ML program. It determines the magnitude of the complex input vector and clips the output magnitude if it is greater than a threshold. The polar_clip has a single input stream of complex 16-bit samples, and a single output stream whose underlying samples are also complex 16-bit elements.

Classifier is an AIE-ML program. It determines the quadrant of the complex input vector and outputs a single real value depending which quadrant. The input interface is a cint16 stream and the output is a int32 window. 

S2MM is a HLS kernel. It performs Stream to Memory Map HLS kernel to feed output result data from AI Engine classifier kernel to DDR via the PL DMA.

Download the AMD 2023.2 tutorial from:

https://github.com/Xilinx/Vitis-Tutorials

Select and download branch [2023.2] into file:

Vitis-Tutorials-2023.2.zip

Unzip it to directory:

~/work/Vitis-Tutorials-2023.2

Copy the directory with the tutorial:

~/work/Vitis-Tutorials-2023.2/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration

to a new directory (just to keep the original unchanged):

~/work/Vitis-Tutorials-2023.2/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration_1

Open Ubuntu console and follow steps 1. to 8. to compile and package the system for HW test on the te0950 board:

1. Change directory to 05-AI-engine-versal-integration_1.
2. Source definitions of system variables required by compilers.
3. Compile AIE-ML programs and use for description of connections the cpp. Result of compilation is the AIE-ML library libadf.a
4. Compile HLS datamovers with v++ compiler. Result of compilation are the xo and s2mm.xo HW archives.
5. Link the AIE-ML library libadf.a, datamovers mm2s.xo and s2mm.xo with the platform te0950_03_300_pfm into new archive tutorial.xsa. Connections are defined in in system.cfg.
6. Compile and link the A72 sw into the PS executable application exe.
7. Package host.exe , ../tutorial.xsa , ../libadf.a to ./sw/a.xclbin and create ./sw/sd_card.img image for the SD card.

############ 1. Change directory to 05-AI-engine-versal-integration_1.

cd ~/work/Vitis-Tutorials-2023.2/AI_Engine_Development/AIE-ML/Feature_Tutorials/05-AI-engine-versal-integration_1

############ 2. Source definitions of system variables required by compilers.

source /tools/Xilinx/Vitis/2023.2/settings64.sh
source /home/devel/work/dpucv2dx8g-trd/te0950_pfm/environment-setup-cortexa72-cortexa53-xilinx-linux

############ 3. Compile AIE-ML programs and use for description of connections the cpp. Result of compilation is the AIE-ML library libadf.a

v++ -c --mode aie --target hw --platform /home/devel/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm/te0950_300_pfm.xpfm --include "$XILINX_VITIS/aietools/include" --include "./aie" --include "./data" --include "./aie/kernels" --include "./" --work_dir=./Work aie/graph.cpp

############ 4. Compile HLS datamovers with v++ compiler. Result of compilation are the xo and s2mm.xo HW archives.

v++ -c -t hw --platform /home/devel/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm/te0950_300_pfm.xpfm --save-temps -k s2mm pl_kernels/s2mm.cpp -o s2mm.xo

v++ -c -t hw --platform /home/devel/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm/te0950_300_pfm.xpfm --save-temps -k mm2s pl_kernels/mm2s.cpp -o mm2s.xo

############ 5. Link the AIE-ML library libadf.a, datamovers mm2s.xo and s2mm.xo with the platform te0950_03_300_pfm into new archive tutorial.xsa. Connections are defined in in system.cfg. 

v++ -l --platform /home/devel/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm/te0950_300_pfm.xpfm s2mm.xo mm2s.xo libadf.a -t hw --save-temps -g --config system.cfg -o tutorial.xsa

############ 6. Compile and link the A72 sw into the PS executable application exe.

cd ./sw
aarch64-linux-gnu-g++ -std=c++1y -DVITIS_PLATFORM=tutorial_pfm -D__USE_XOPEN2K8 -I/tools/Xilinx/Vitis_HLS/2023.2/include/ -I/home/devel/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux/usr/include/xrt/ -O2 -g -Wall -c -fmessage-length=0 --sysroot=/home/devel/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux -o host.o host.cpp

aarch64-linux-gnu-g++ -o host.exe host.o -luuid -lxrt_coreutil -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L/home/devel/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux/usr/lib/ --sysroot=/home/devel/work/dpucv2dx8g-trd/te0950_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
cd ..

############ 7. Package host.exe ../tutorial.xsa ../libadf.a to ./sw/a.xclbin and create ./sw/sd_card.img image for the SD card.

cd ./sw
v++ --package -t hw     -f /home/devel/work/dpucv2dx8g-trd/te0950_pfm/te0950_300_pfm/export/te0950_300_pfm/te0950_300_pfm.xpfm  -o ./a.xclbin   --package.rootfs=/home/devel/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux/rootfs.ext4     --package.image_format=ext4     --package.boot_mode=sd     --package.kernel_image=/home/devel/work/dpucv2dx8g-trd/te0950_platform/sw/te0950/images/linux/Image     --package.defer_aie_run     --package.sd_file host.exe ../tutorial.xsa ../libadf.a
cd ..

Create SD card from file img.

Boot the TE0950 board from the SD card with output to the terminal.

Execute the host.exe applicaton.

Halt OS by halt Boare can be disconnected from PC and Power-OFF.

############ TE0950 board console
dmesg -n 4 && echo "Hide DRM messages..."
cd /run/media/*1
export XILINX_XRT=/usr
./host.exe a.xclbin

This is TE0950-03 board console listing:

root@te0950:~# dmesg -n 4 && echo "Hide DRM messages..."
Hide DRM messages...
root@te0950:~# export XILINX_XRT=/usr
root@te0950:~# cd /run/media/*1
root@te0950:/run/media/mmcblk1p1# ./host.exe a.xclbin
XAIEFAL: INFO: Resource group Avail is created.
XAIEFAL: INFO: Resource group Static is created.
XAIEFAL: INFO: Resource group Generic is created.
Input memory virtual addr 0x0xffff9c232000x
Output memory virtual addr 0x0xffff9c231000x
run mm2s
run s2mm
graph run
graph end
TEST PASSED
Releasing remaining XRT objects...
root@te0950:/run/media/mmcblk1p1#

The TEST PASSED message indicates correct result.

Reboot the OS or halt the TE0950 board before next execution of the same example. 

############ reboot TE0950 board 
reboot
############ halt TE0950 board 
halt
############ remove SD card, close console, switch OFF TE0950 board

After halt command, the SD card can be removed and the TE0950 board can be switched OFF.

This AIE-ML integration flow example can be used as initial template for your AIE-ML development on the te0950-03 board.

The integrated system with AI-ML section has this internal structure:

Structure of the system with AIE-ML engine application

The integrated system with AI-ML section has this internal structure:

The AIE-ML section contains  the interpolator, polar_clip and classifier programs running on three interconnected AIE-ML engines. The AIE-ML part of the integrated design is running with the 1GHz clock.

The Vitis part contains integrated HLS data movers mm2s and s2mm HW IP cores. These cores perform the input and output memory mapped DMA and drive two interrupt signals. Both cores are implemented in the PL part of the device and use the default 300 MHz clock of the te0950_03_300 platform. 

Display on X11 terminal

System can be connected to the X11 terminal running on your PC Ubuntu with connection via Ethernet by Ubuntu PuTTY communication tool.

• Find Ethernet IP address of your board by typing ifconfigcommand in PetaLinux terminal.
  In PC Ubuntu OS, open PuTTY
  In PuTTY, set  Ethernet IP of your board.
  In PuTTY, select checkbox SSH->X11->Enable X11 forwarding.
• In PuTTY, open PetaLinux terminal and login as:
  user: root
  pswd: root.
• In opened PetaLinux PuTTY terminal, start X11 desktop x-session-managerby typing:

sh-5.1# x-session-manager &

• Use PC Ubuntu mouse and keyboard. Click on X11 icon (A Unicode capable rxvt). Terminal opens as an X11 graphic window.
• In X11 terminal rxvt, use Ubuntu PC keyboard and type:

sh-5.1# cd /run/media/sd-mmcblk1p1/
sh-5.1# ./test_vadd binary_container_1.xclbin

The application test_vadd should run with this output:

INFO: Reading binary_container_1.xclbin
Loading: 'binary_container_1.xclbin'
Trying to program device[0]: edge
Device[0]: program successful!
TEST PASSED

The application test_vadd has been started from the X11 xrvt terminal emulator. 

• Close the rxvt terminal emulator by click ”x” icon (in the upper right corner) or by typing:

sh-5.1# exit

• In X11, click Shutdown icon to safely close PetaLinux running on the test board.System on the test board is halted.
• The SD card can be safely removed from the board.
• Close the PC USB terminal application.
• The TE0950-03 board can be disconnected from power.

Display Test Pattern and Test USB Camera

Complete video chain can be tested with output to the X11 desktop.

To display the test pattern, use this gstreamer command: 

sh-5.1# gst-launch-1.0 videotestsrc ! ximagesink

 To display USB camera video, use this gstreamer command:

sh-5.1# gst-launch-1.0 v4l2src device=/dev/video0 ! videoconvert ! ximagesink

Test pattern is displayed on remote PC X11 desktop

Full HD video from USB camera is displayed as Full HD on remote PC X11 desktop.

References

1. TE0950, Vitis 2023.2.1, Extensible Platform
2. TE0950, Vitis 2023.2.1, Integration of DPUCZDX8G
3. TE0950, Vitis 2023.2.1, Integration of DPUCV2DX8G
4. TE0950, Vitis 2023.2.1, AI 3.0 Models for DPUCZDX8G
5. TE0950, Vitis 2023.2.1, AI 3.5 Models for DPUCV2DX8G
6. AMD Versal™ AI Edge Evalboard with VE2302 device, 8 GB DDR4 SDRAM, 15 x12 cm
   https://shop.trenz-electronic.de/en/TE0950-03-EGBE21C-AMD-Versal-AI-Edge-Evalboard-with-VE2302-device-8-GB-DDR4-SDRAM-15-x12-cm?path=Trenz_Electronic/Development_Boards/TE0950/Reference_Design/2023.2/test_board
7. TE0950 Basic Linux Example archive for Vivado 2023.2.1, build 4, from 31.05.2024 - Versal device 
   https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Development_Boards/TE0950/Reference_Design/2023.2/test_board/TE0950-test_board-vivado_2023.2-build_4_20240531092954.zip
8. TE0950 Basic Linux Example archive for Vivado 2023.2.1, build 4, from 31.05.2024 - Artix device
   https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Development_Boards/TE0950/Reference_Design/2023.2/test_board/TE0950-test_board_artix-vivado_2023.2-build_4_20240531084104.zip