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PS Peripherals

 

MIO PinMapped toPull up/downNotes
0GPIOUpRTC Interrupt
1QSPI0  
2QSPI0Down 
3QSPI0Down 
4QSPI0DownOverride to up on base for bootmode change
5QSPI0Up 
6QSPI0Down 
7GPIODownOn-board LED
8CAN1 TXDDownCAN transceiver in SBC
9CAN1 RXD CAN transceiver in SBC
10SPI1 MOSI SBC SPI Bus
11SPI1 MISO SBC SPI Bus
12SPI1 SCLK SBC SPI Bus
13SPI1 SS0 SBC SPI Bus
14I2C0 SCLUpOn-board RTC, and EEPROM
15I2C0 SDAUpOn-board RTC, and EEPROM

Recommended Peripheral mapping for MIO Voltage bank 0.

 

PL Peripherals

Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's. PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

 

PS and PL Banks

BankVCCIOB2B I/O PinsNotes
5003.3V0 
501USER36Vref is connected to resistor divider to support HSTL18
13USER48Differential routing
333.3V33Single ended routing
343.3V0Ethernet PHY's
353.3V42Single ended routing
03.3V4JTAG, note 3 pins can be used as input only from PL Fabric

 

Clock sources

DesignatorDescriptionFrequencyUsed as
U14MEMS Oscillator33.3333MHzPS_CLK
U5MEMS Oscillator25MHzEthernet PHY Clock
U7RTC32.768KHzUsed by RTC, CLKOUT of RTC not connected

 

LED's

DesignatorColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenPL pin V18HighLVCMOS33

 

XADC Usage

XADC PinConnected toNotes
VP_0SBC MUX_OUTResistor divider to adjust ADC Range
VN_0GND 
AD0B2B 
AD1B2B 
AD3B2B 
AD4B2B 
AD5B2B 
AD7PB2B 
AD7NGND 
AD8B2B 
AD9B2B 
AD10B2B 
AD12B2B 
AD13B2B 
AD14B2B 
AD15B2B 

XADC is used with internal reference option.

Note the XADC capable pins are not routed differentially to the B2B connector. The performance and usability of the XADC must be evaluated.

SBC

SBC - System Basis Chip MC33908

 

SBC NameConnectedNotes
VDDIO3.3VI/O Voltage fix 3.3V
VCCAJ1.17 B2BNot used on board, external PNP Transistor not used, max 100mA
VAUX-Not connected, not used
SELECT5K1 to VPRESelect 3.3V for VCCA Supply
MUX_OUTXADC 
CAN RXDMIO9 
CAN TXDMIO8 
LIN RXDPL Y14LIN Soft IP should be implemented in PL Fabric
LIN TXDPL AA14 
MOSIMIO10 
MISOMIO11 
SCKMIO12 
NCSMIO13 
DEBUGJ1.18 B2B11K Pull-down on module, defaults to debug mode DISABLED
IO_0J1.7 B2B 
IO_1J1.9 B2B 
IO_2J1.11 B2B 
IO_3J1.13 B2B 
IO_4J1.8 B2B 
IO_5J1.10 B2B 
INTBJ1.12 B2BIf connection to MIO or PL is needed must be implemented on base board
FS0BJ1.16 B2B 
RSTBJ1.14 B2BAlso forces system Reset
CANHJ1.2 B2B120R terminator on board, EMI and ESD should be on base board
CANLJ1.4 B2B 
LINJ1.20 B2BAny termination, ESD and EMI circuits should be on base board

 

Note: the availability LIN depends on the Module version and assembly option.

Ethernet

 

 

 ETH1ETH2PullupNotes
TD+J3.58J3.on-board 
TD-J3.56J3.on-board 
RD+J3.52J3.on-board 
RD-J3.50J3.on-board 
LED1J3.55J3.23on-board 
LED2J3.53J3.21on-board 
LED3J3.51J3.19on-board 

 

Document Change History

DateRevisionAuthorsDescription
2015-05-10 Work in progress
 

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