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Table of Contents

Overview

 

The Trenz Electronic TE0808 is an industrial-grade MPSoC UltraSoM integrating a Xilinx Zynq UltraScale+, 4 x 4 Gbit (256 MByte) DDR4 SDRAM with 16-bit databus width, 2 x 256 MBit (32 MByte) Flash memory for configuration and operation, 20 Gigabit transceivers, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

Current TE0808 boards are equipped with ES1 silicon. Erratas and functional restrictions may exist, please check Xilinx documentation and contact your local Xilinx FAE for restrictions.

Block Diagram

Figure 1: TE0808-03 Block Diagram

Main Components

           

Figure 2: TE0808-03 MPSoC module

  1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
  2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. 12A PowerSoC DC-DC converter, U4
  9. Quartz crystal, Y1
  10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
  11. 10-channel programmable clock generator, U5
  12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Quartz crystal, Y2
  17. 256 Mbit serial NOR Flash memory, U7
  18. 256 Mbit serial NOR Flash memory, U17

Key Features

  • MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
  • Memory
    - 64-Bit DDR4, 8 GByte maximum
    - Dual SPI boot Flash in parallel, 512 MByte maximum
  • User I/O
    - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
    - Serial transceiver: 4 x GTR + 16 x GTH
    - Transceiver clocks inputs and outputs
    - PLL clock generator inputs and outputs
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin
  • Si5345 - 10 output PLL
  • All power supplies on board, single 3.3V power source required
    - 14 on-board DCDC regulators and 13 LDOs
    - LP, FP, PL separately controlled power domains
  • Support for all boot modes (except NAND) and scenarios
  • Support for any combination of PS connected peripherals

Initial Delivery State

 Storage device name

Content

Notes

SPI Flash main array

Not programmed

-

eFUSE Security

Not programmed

-

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0808 MPSoC UltraSoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq Ultrascale+ MPSoC like I/O banks, interfaces and Gigabit transceivers
or to the on-board ICs of the UltraSoM.

B2B connector J1
Signal typeBank / ICSchematic names / Connector pinsConnector pin count / I/O'sVCCIODirectionNotes
GTH lane

Bank 230 (GTH)

4 GTH lanes

B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4

B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10

B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16

B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22

 16 pins - Input/OutputGTH-lanes, each composed of two LVDS-pairs

GTH lane

Bank 229 (GTH)

4 GTH lanes

B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28

B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34

B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40

B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46

 16 pins - Input/OutputGTH-lanes, each composed of two LVDS-pairs

GTH lane

Bank 228 (GTH)

4 GTH lanes

B228_RX3_P, B228_RX3_N, pins J1-27, J1-29
B228_TX3_P, B228_TX3_N, J1-26, J1-28

B228_RX2_P, B228_RX2_N, pins J1-33, J1-35
B228_TX2_P, B228_TX2_N, J1-32, J1-34

B228_RX1_P, B228_RX1_N, pins J1-39, J1-41
B228_TX1_P, B228_TX1_N, J1-38, J1-40

B228_RX0_P, B228_RX0_N, pins J1-45, J1-47
B228_TX0_P, B228_TX0_N, J1-44, J1-46

16 pins-Input/OutputGTH-lanes, each composed of two LVDS-pairs
LVDS pair

Bank 66 (HP)
LVDS pairs 1 ... 24

B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N
48 I/O's

VCCO66
pins J1-90, J1-120

Input/OutputVCCO max. 1.8V
usable as single-ended I/O's
Single ended I/OBank 66 (HP)B_66_T0 ... B_66_T3
pins J1-147, J1-145, J1-143, J1-141
4 I/O's

VCCO66

pins J1-90, J1-120
Input/OutputVCCO max. 1.8V
Reference Input VoltageBank 66 (HP)VREF_66, pin J1-1081 pin-Input-
Power RailU4 (DCDC)PL_DCIN,
pins J1-151, J1-153, J1-157, J1-159
4 pins-Input-
Internal voltage levelU19 (DCDC)PL_1V8, pins J1-91, J1-1212 pins-Output1.8V nominal output
B2B connector J2
Signal typeBank / IC

Schematic names / Connector pins

Connector pin count / I/O'sVCCIODirectionNotes
Reference Clock signalU5 (programmable PLL)

CLK0_P, CLK0_N, pins J2-3, J2-1
CLK7_P, CLK7_N, pins J2-7, J2-9
CLK8_P, CLK8_N, pins J2-13, J2-15

6 pins-Output

output from Si5351A-B-GM
programmable PLL clock generator

LVDS-pairs

Reference Clock signalU5 (programmable PLL)

IN1_P, IN1_N, pins J2-3, J2-1

2 pins-Input

input to Si5351A-B-GM
programmable PLL clock generator

LVDS-pair

Reference Clock signalBank 505 (GTR)B505_CLK0_P, B505_CLK0_N, pins J2-10, J2-12
B505_CLK1_P, B505_CLK1_N, pins J2-16, J2-18
4 pins-Input

reference clock input to MPSoC's bank

LVDS-pairs

Reference Clock signalBank 128 (GTH)B128_CLK1_P, B128_CLK1_N, pins J2-22, J2-242 pins-Input

reference clock input to MPSoC's bank

LVDS-pair

GTH lane

Bank 128 (GTH)

4 GTH lanes

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

16 pins-Input/Output

GTH-lanes, each composed of two LVDS-pairs

GTR lane

Bank 505 (GTR)

4 GTR lanes

B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51

B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57

B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63

B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69

16 pins-Input/OutputGTR-lanes, each composed of two LVDS-pairs
Control lineBank 503 (PSCONFIG)

DONE, pin J2-116 (indicated by red LED D1)
PROG_B, pin J2-100
INIT_B, pin J2-98
SRST_B, pin J2-96
MODE0, pins J2-109
MODE1, pins J2-107
MODE2, pins J2-105
MODE3, pins J2-103
ERR_OUT, pin J2-88
ERR_STATUS, pin J2-86
PUDC_B, pin J2-127

11 I/O's

PS_1.8V
(PUDC_B pulled-up to PL_1V8)

Input/Output-
JTAG InterfaceBank 503 (PSCONFIG)

TCK, pin J2-120
TDI, pin J2-122
TDO, pin J2-124
TMS, pin J2-126

4 I/O'sPS_1.8VInput/Output-
Analog input
differential pair
MPSoC ADCV_P, V_N, pins J2-113, J2-115

DX_P, DX_N, pins J2-119, J2-121

 

4 pins-Input/OutputLVDS-pairs
Control lineU5 (programmable PLL)

PLL_FINC, pin J2-81
PLL_LOLN, pin J2-85
PLL_SEL0, pin J2-93
PLL_SEL1, pin J2-87
PLL_FDEC, pin J2-94
PLL_RST, pin J2-59
PLL_SCL, pin J2-90 (I²C interface)
PLL_SDA, pin J2-92 (I²C interface)

8 I/O's1.8VInput/Output

Control interface to Si5351A-B-GM
programmable PLL clock generator

Control lineU44 (DCDC)
U10 (DCDC)

EN_PSGT, pin J2-84
PG_PSGT, pin J2-82

2 I/O'sEN_PSGT: max. 'DCDCIN',
PG_PSGT: extern pull-up needed, max. 6V
Input/Output"Enable"- and corresponding
"Power Good"-Signal 
Control lineU39 (DCDC)
U30 (DCDC)
EN_FPD, pin J2-102
PG_FPD, pin J2-110
2 I/O'sEN_FPD: max. 'DCDCIN',
PG_FPD: pulled-up to 'DCDCIN'
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control line

U29 (DCDC)
U15 (DCDC)

EN_LPD, pin J2-108
LP_GOOD, pin J2-106

2 I/O'sEN_LPD: max. 7V,
LP_GOOD: pulled-up to 'LP_DCDC'
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control line

U40 (DCDC)
U31 (DCDC)

EN_DDR, pin J2-112
PG_DDR, pin J2-114

2 I/O'sEN_DDR: max. 'DCDCIN',
PG_DDR: pulled-up to 'DCDCIN'
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control lineU38 (DCDC)
U38 (DCDC)

EN_PLL_PWR, pin J2-77
PG_PLL_1V8, pin J2-80

2 I/O'sEN_PLL_PWR: max. 7V,
PG_PLL_1V8: extern pull-up needed, max. 6V
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control lineU43 (DCDC)
U13 (DCDC)

EN_GT_L, pin J2-79
PG_GT_L, pin J2-97

2 I/O'sEN_GT_L: max. 'GT_DCDC',
PG_GT_L: extern pull-up needed, max. 6V
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control lineU42 (DCDC)
U28 (DCDC)

EN_GT_R, pin J2-95
PG_GT_R, pin J2-91

2 I/O'sEN_GT_R: max. 'GT_DCDC',
PG_GT_R: extern pull-up needed, max. 6V
Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control lineU4 (DCDC)
U19 (DCDC)

EN_PL, pin J2-101
PG_PL, pin J2-104

2 I/O's

EN_PL connected to 'PL_DCIN'
PG_PL: extern pull-up needed, max. 'GT_DCDC'

Input/Output

"Enable"- and corresponding
"Power Good"-Signal

Control lineU41
(voltage monitor IC)
MR, pin J2-831 I/Omax. 'LP_DCDC'InputManual-reset (low-active signal).

Leave unconnected or connect
to VDD (LP_DCDC) when unused.

Power RailU24/U31/U30/U23
(DCDC)
DCDCIN
pins J2-154, J2-156, J2-158, J2-160,
       J2-153, J2-155, J2-157, J2-159
8 pins-Input-
Power RailU20/U41 (DCDC)LP_DCDC, pins J2-138, J2-140, J2-142, J2-1444 pins-Input-
Power RailBank 503 (PSCONFIG)PS_BATT, pin J2-1251 pin-Input-
Internal voltage levelU15 (DCDC)PS_1V8, pin J2-991 pin-Output1.8V nominal output
Internal voltage levelU31 (DCDC)DDR_1V2, pin J2-1351 pin-Output1.2V nominal output
B2B Connector J3
Signal typeBank / ICSchematic names / Connector pinsConnector pin count / I/O'sVCCIODirectionNotes
LVDS pair

Bank 48 (HD)
LVDS pairs 1 ... 12

B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N

24 I/O's

VCCO48
pins J3-15, J3-16

Input/Output

VCCO max. 3.3V
usable as single-ended I/O's

LVDS pair

Bank 47 (HD)
LVDS pairs 1 ... 12

B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N

24 I/O's

VCCO47
pins J3-43, J3-44

Input/Output

VCCO max. 3.3V
usable as single-ended I/O's

Reference Clock signalU5 (programmable PLL)IN2_P, IN2_N, pins J3-66, J3-682 pins-Input

input to Si5351A-B-GM
programmable PLL clock generator

LVDS-pair

Reference Clock signalBank 228 (GTH)

B228_CLK0_P, B228_CLK0_N, pins J3-10, J3-12

2 pins-Input

reference clock input to MPSoC's bank

LVDS-pairs

Reference Clock signalBank 229 (GTH)B229_CLK0_P, B229_CLK0_N, pins J3-22, J3-242 pins-Input

reference clock input to MPSoC's bank

LVDS-pairs

Reference Clock signalBank 230 (GTH)B230_CLK1_P, B230_CLK1_N, pins J3-10, J3-122 pins-Input

reference clock input to MPSoC's bank

LVDS-pairs

MIOBank 500 (PSMIO)MIO13 ... MIO2513 I/O'sPS_1V8Input/Output-
MIOBank 501 (PSMIO)MIO26 ... MIO5126 I/O'sPS_1V8Input/Output-
MIOBank 502 (PSMIO)MIO52 ... MIO7726 I/O'sPS_1V8Input/Output-
Power RailU38/U35/U36/U21/U22
(DCDC)

GT_DCDC, pins J3-157, J3-158, J3-159, J3-160

4 pin-Input-
Power RailU5 (programmable PLL)PLL_3V3, pin J3-1521 pin-Input3.3V nominal input
Internal voltage levelU38 (DCDC)SI_PLL_1V8, pin J3-1511 pin-Output1.8V nominal output
Internal voltage levelU15 (DCDC)

PS_1V8, pins J3-147, J3-148

2 pins-Output1.8V nominal output
B2B Connector J4
Signal typeBank / ICSchematic names / Connector pinsConnector pin count / I/O'sVCCIODirectionNotes
LVDS pair

Bank 64 (HP)
LVDS pairs 1 ... 24

B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

48 I/O's

VCCO64
pins J4-58, J4-106

Input/Output

VCCO max. 1.8V
usable as single-ended I/O's

LVDS pair

Bank 65 (HP)
LVDS pairs 1 ... 24

B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

48 I/O's

VCCO65
pins J4-69, J4-105

Input/Output

VCCO max. 1.8V
usable as single-ended I/O's

Single ended I/OBank 64 (HP)

B_64_T0 ... B_64_T3
pins J4-8, J4-6, J4-4, J4-2

4 I/O's

VCCO64
pins J4-58, J4-106

Input/Output

VCCO max. 1.8V

Single ended I/OBank 65 (HP)

B_65_T0 ... B_65_T3
pins J4-7, J4-5, J4-3, J4-1

4 I/O's

VCCO65
pins J4-69, J4-105

Input/Output

VCCO max. 1.8V

Reference Input Voltage

Bank 64 (HP)VREF_64, pin J4-881 pin-Input-
Reference Input VoltageBank 65 (HP)VREF_65, pin J4-151 pin-Input-

Table 2: B2B Connector pin assignment of the TE0808-03 UltraSoM

For detailed information about the B2B pin-out, please refer to the Pin-out table.

Quad-SPI Flash memory

The TE0808-03 UltraSoM is equipped with two Micron Serial NOR Flash Memory with 256 Mbit (32 Mbyte) storage capacity each. The flash memory ICs with the schematic designators U7 and U17 are connected to bank 500 (PSMIO) of the Zynq MPSoC module via QSPI interface.

Following table shows the mapping of the MIO-pins to the flash memory ICs.

Flash Memory IC U7 Flash Memory IC U7
MIOFunctionNotesMIOFunctionNotes
0CLKClock7CS

Chip-select,

low-active, pulled-up to PS_1V8
1DQ1Serial Data (Output and I/O)8DQ0Serial Data (Input and I/O)
2DQ2Serial Data (Input and I/O)9DQ1Serial Data (Output and I/O)
3DQ3Serial Data (Input and I/O)10DQ2Serial Data (Input and I/O)
4DQ0Serial Data (Input and I/O)11DQ3Serial Data (Input and I/O)
5CS

Chip-select,
low-active, pulled-up to PS_1V8

12CLKClock

Table 3: Flash memory QSPI-interface

DDR4-2400 SDRAM

The TE0808-03 UltraSoM is equipped with with four Nanya NT5AD256M16B2-GN DDR4-2400 SDRAM modules with 4 Gbit (256 MByte) memory density. The SDRAM modules are connected to the PS DDR controller (bank 504) with 16 bit databus width respectively.

 

LEDs

TE0808 has one red LED (D1) which reflects MPSoC's 'DONE' signal. This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.

Clocking

Programmable Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

Input/OutputConnected toFrequencyNotes
IN0On-board Oscillator25.000000 MHz-
IN1B2B ConnectorUserAC decoupling required on base
IN2B2B ConnectorUserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
OUT0B2B ConnectorUserDefault off
OUT1B230 CLK0UserDefault off
OUT2B229 CLK1UserDefault off
OUT3B228 CLK1UserDefault off
OUT4B505 CLK2UserDefault off
OUT5B505 CLK3UserDefault off
OUT6B128 CLK0UserDefault off
OUT7B2B ConnectorUserDefault off
OUT8B2B ConnectorUserDefault off.
OUT9IN3UserDefault off
XA/XBQuartz50.000 MHz-
ClockFrequencyFPGA PinConnected To
PS_CLK33.333333 MHzP20MEMS Oscillator
PS_PAD (RTC)32.768 kHzR22/R23Quartz crystal

Power and Power-On Sequence

The TE0808-03 module with the Xilinx Zynq Ultrascale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management is achieved by establishing Power Domains for power isolation. The Zynq Ultrascale+ MPSoC is composed of multiple power domains, whereby each power domain requires their particular extern DCDC converters.

The Processing System contains three Power Domains:

  • Battery Power Domain, needed for BBRAM and RTC
  • Full-Power Domain, needed for Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity
  • Low-Power Domain, needed for Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

The following diagram shows the sequence of enabling the on-board DCDC converters dedicated to the particular Power Domains and powering up the needed voltages.

On the TE0808-03 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

  • Full-Power Domain, supplied by power rail 'DCDCIN'
  • Low-Power Domain, supplied by power rail 'LP_DCDC'
  • Programmable Logic, supplied by power rail 'PL_DCIN'
  • Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signal. The power rail 'GT_DCDC' generates the supply voltages for the high speed Gigabit Transceivers units of the Zynq Ultrascale+ MPSoC.

For the absolute maximum ratings and the recommended operating conditions of the power rails, see section 'Technical Specifications'.

 

 

Figure 3: TE0808-03 Power-On sequence diagram

B2B connectors

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Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.37VTPS82085SIL/EN63A0QI data sheet
DCDCIN-0.37VTPS82085SIL/TPS51206PSQ data sheet
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.37VTPS82085SIL data sheet
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally

Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
('EN_PLL_PWR', 'EN_LPD')
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

–40

125

°C

TPS82085SIL data sheet

Recommended Operating Conditions

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN1.86VTPS82085SIL data sheet
DCDCIN3.16VTPS82085SIL/TPS51206PSQ data sheet
LP_DCDC2.03.6VTPS3106K33DBVR data sheet
GT_DCDC1.86VTPS82085SIL data sheet
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.143.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 4mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

-40 ... 125 TPS82085SIL data sheet

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

17 g - Plain module

Revision History

Hardware Revision History

 DateRevision

Notes

Link to PCNDocumentation Link
-03Second production release-TE0808-03
2016-03-0902First production release-TE0808-02
-01Prototypes--

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Document Change History

 Date

Revision

ContributorsDescription
2017-02-06
Jan KumannInitial document.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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