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Table of Contents
Overview
Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
Within the complete module only Automotive components are installed.
All this in a compact 6 x 6 cm form factor, at the most competitive price.
Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.
Key Features
- Xilinx XA7Z020-1CLG484Q (Automotive)
- Rugged for shock and high vibration
- Dimensions: 6 x 6 cm
- Temperature range: Automotive
- Dual-Core ARM Cortex-A9 MPCore
- 2 x 100 MBit Ethernet transceiver (PHY)
- 512 MByte DDR3L SDRAM, 16-bit-wide
- 16 MByte QSPI Flash memory (with XiP support)
- Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
- 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
- CAN transceiver (PHY)
- 12 V power supply with watchdog
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- Three user LEDs
- Evenly-spread supply pins for good signal integrity
Other assembly options for cost or performance optimization plus high volume prices available on request.Depending on the customer design, additional cooling might be required.
Block Diagram
TE0728 block diagram
Main Components
TE0728 main components
- 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
- Xilinx Automotive XA7Z020-1CLG484Q ,U2
- 100 MBit Ethernet transceiver DP83848, U3
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
- Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
- 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
- Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
- 100 MBit Ethernet transceiver DP83848MPHPEP, U10
- 64 Kbit I2C EEPROM, 24LC64, U11
- Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
- 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
- Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
- Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
- CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM2
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM3
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM1
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
Quad SPI Flash | U13 | Empty |
| DDR3 SDRAM | U1 | Empty |
| 24LC64 | U11 |
Initial delivery state of programmable devices on the module
Control Signals
Boot Process
MODE Signal State | Boot Mode |
|---|---|
High or open | QSPI |
Boot process.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|---|---|---|---|
| 13 | JM1 | 48 | VCCO_13 | |
| 500 | JM1 | 4 | 3.3V | |
| 33 | JM3 | 34 | 3.3V | |
| 35 | JM3 | 20 | 3.3V | |
| 35 | JM2 | 22 | 3.3V | |
| 501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
General PL I/O to B2B connectors information
JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
|---|---|
| TMS | JM2-12 |
| TDI | JM2-10 |
| TDO | JM2-8 |
| TCK | JM2-6 |
JTAG pins connection
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.
On-board Peripherals
| Chip/Interface | IC | PS7 Peripheral | Notes |
|---|---|---|---|
| SPI Flash | S25FL127SABMFV10 | QSPI0 | 16 MByte Flash |
| I2C EEPROM | 24LC64 | I2C0 | 64 KByte EEPROM |
| RTC I2C | RV-3029 | I2C0 | |
| RTC Interrupt | RV-3029 | GPIO - MIO0 | |
| User LED | LED Green | GPIO - MIO7 |
On board peripherals
16 MByte Quad SPI Flash MemoryTable 5: On board Peripherals
On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.
| MIO Pin | Schematic | U13 Pin | Notes |
|---|---|---|---|
| MIO1 | SPI_CS | A1 | |
| MIO2 | SPI_DQ0/M0 | A2 | |
| MIO3 | SPI_DQ1/M1 | F6 | |
| MIO4 | SPI_DQ2/M2 | E4 | |
| MIO5 | SPI_DQ3/M3 | A3 | |
| MIO6 | SPI_SCK/M4 | A4 |
Quad SPI interface MIOs and pins
Supply Voltage: 2.7V to 3.6VTable 6: Quad SPI interface MIOs and pins
Temperature Range:
- Industrial (-40°C to +85°C)
- Industrial Plus (-40°C to +105°C)
- Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
- Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
RTC I2C
The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.
| MIO Pin | Schematic | U7 Pin | Notes |
|---|---|---|---|
| MIO15 | SDA | 5 | On-board RTC, and EEPROM |
| MIO14 | SCL | 4 | On-board RTC, and EEPROM |
I2C interface MIOs and pins
I2C EEPROM
The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
| MIO Pin | Schematic | U11 Pin | Notes |
|---|---|---|---|
| MIO15 | SDA | 3 | On-board RTC, and EEPROM |
| MIO14 | SCL | 1 | On-board RTC, and EEPROM |
I2C EEPROM interface MIOs and pins
LEDs
| Schematic | Color | Connected to | Active Level | IO Standard |
|---|---|---|---|---|
| D9 | Green | DONE | Low | not applicable |
| D8 | RED | MIO7 | High | not applicable |
| D4 | Green | PL pin V18 | High | LVCMOS33 |
On-board LEDs
512 Mbyte DDR3L SDRAM
The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number: NT5CC256M16DP Nanya
- Supply voltage: 1.35V
- Speed: 1600 Mbps
- NOR Flash
- Temperature: -40°C ~95°C
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet DP83848-EP are provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.
PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.
Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
| Schematic | ETH1 | ETH2 | Pullup | Notes |
|---|---|---|---|---|
| CTREF | J3-57 | J3-25 | Magnetics center tap voltage | |
| TD+ | J3-58 | J3-28 | on-board | |
| TD- | J3-56 | J3-26 | on-board | |
| RD+ | J3-52 | J3-22 | on-board | |
| RD- | J3-50 | J3-20 | on-board | |
| LED1 | J3-55 | J3-23 | on-board | |
| LED2 | J3-53 | J3-21 | on-board | |
| LED3 | J3-51 | J3-19 | on-board | |
| POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
| RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
Ethernet PHY to Zynq SoC connections
It is recommended to add IOB TRUE constraint for the MII Interface pins.Table 10: Ethernet PHY to Zynq SoC connections.
When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
CAN Transceiver
The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .
| MIO Pin | Schematic | U16 Pin | Notes |
|---|---|---|---|
| MIO8 | D | 1 | |
| MIO9 | R | 4 |
CAN Tranciever interface MIOs
Low Quiescent Current Programmable Delay Supervisory Circuit
The TPS3808G01-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the useradjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
The TPS3808G01-Q1 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808G01-Q1 has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications.
Low Dropout Linear Regulator
The TPS74801-Q1 low-dropout (LDO) provides an easy-to-use robust power management solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.
A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.
Clock Sources
| IC | Description | Frequency | Used as |
|---|---|---|---|
| U14 | MEMS Oscillator | 50 MHz | PS PLL clock |
| U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock |
| U7 | RTC (internal oscillator) | 32.768 KHz | Used by RTC, CLKOUT of RTC not connected |
Osillators
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3.5 A for system startup is recommended.
Power Consumption
| Power Input Pin | Typical Current |
|---|---|
| VIN | TBD* |
Power Consumption
* TBD - To Be Determined
Power Distribution Dependencies
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draw.io
Power Distribution
Power-On Sequence
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Power Sequency
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.
Voltage Monitor Circuit
Power Rails
| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
|---|---|---|---|---|---|
| VIN | 1,3 | - | - | Input | |
| VMIO | - | 2 | - | I/O | |
| 3.3V | 19 | 4 | 25,57 | Output | |
1.8V | - | 5 | - | Output |
Module power rails.
Bank Voltages
Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | |
| 501 | VCCO_MIO1_500 | 3.3V | |
| 502 | VCCO_DDR_502 | 1.5V | |
| 13 HR | VCCO_13 | 3.3V | Supplied by the carrier board. JM1 |
| 33 HR | VCCO_33 | 3.3V | Supplied by carrier board. JM3 |
| 34 HR | VCCO_34 | 3.3V | |
| 35 HR | VCCO_35 | 3.3V | Supplied by the carrier board. JM2,JM3 |
Zynq SoC bank voltages.
Board to Board Connectors
6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2
Absolute Maximum Ratings
Processing System(PS)
| Symbols | Description | Min | Max | Unit |
|---|---|---|---|---|
| VCCPINT | PS internal logic supply voltage | -0.5 | 1.1 | V |
| VCCPAUX | PS auxiliary supply voltage | -0.5 | 2.0 | V |
| VCCPLL | PS PLL supply | -0.5 | 2.0 | V |
| VCCO_DDR | PS DDR I/O supply voltage | -0.5 | 2.0 | V |
| VPREF | PS input reference voltage | -0.5 | 2.0 | V |
| VCCO_MIO0 | PS MIO I/O supply voltage for HR I/O banks | -0.5 | 3.6 | V |
| VCCO_MIO1 | PS MIO I/O supply voltage for HR I/O banks | 1.71 | 3.45 | V |
PS absolute maximum ratings
Programmable Logic(PL)
| Symbols | Description | Min | Max | Unit |
|---|---|---|---|---|
| VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V |
| VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V |
| VCCPLL | PL PLL supply | -0.5 | 1.1 | V |
| VPREF | PL input reference voltage | -0.5 | 2.0 | V |
| VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V |
| VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
PL absolute maximum ratings
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
| CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
| SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. |
| DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
Module absolute maximum ratings.
Recommended Operating Conditions
Commercial grade: 0°C to +70°C.
Industrial and automotive grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
| CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
| SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. |
| DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
Recommended operating conditions.
Physical Dimensions
Physical dimensions drawing
Module size: 60 mm × 60 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.6 mm.
Physical Dimension
Variants Currently In Production
| Trenz shop TE0728 overview page | |
|---|---|
| English page | German page |
Trenz Electronic Shop Overview
Revision History
Hardware Revision History
| Date | Revision | Note | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 | Prototypes | - | - |
Hardware Revision History
Hardware Revision Number
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
-- | all |
|
Document change history.
Disclaimer
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RoHS
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WEEE
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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