Table of contents
Overview
TEB0707 SC CPLD design for MAX10 with designator U6: 10M08SAU169C8G.
Feature Summary
- Levelshifting/MUX of Signals
- CRUVI Low Speed (J13)
- CRUVI 3.3V signals on High Speed CA, CB, CC (J10, J11, J12)
- JTAG/ UART forward to 4x5 module
- Module control pins
- USR LEDs
- Button and Dips
- Power sequenzing
- IO Voltage selection
Firmware Revision and supported PCB Revision
See Document Change History.
Product Specification
Port Description
VHDL Port name | Direction | Pin | Pullup/Down | Bank Power | Bank | Connected to | Function |
---|---|---|---|---|---|---|---|
X7 | in | C2 | 3.3 V | 1A | J13-2 | CRUVI CA LS signals | |
X1 | in | D1 | 3.3 V | 1A | J13-5 | ||
X3 | in | E4 | 3.3 V | 1A | J13-9 | ||
X4 | out | E3 | 3.3 V | 1A | J13-4 | ||
X6 | out | B1 | 3.3 V | 1A | J13-1 | ||
X0 | out | C1 | 3.3 V | 1A | J13-3 | ||
X2 | out | E1 | 3.3 V | 1A | J13-7 | ||
X5 | in | F1 | 3.3 V | 1A | J13-8 | ||
JTAGEN | --- | E5 | down (external) | 3.3V | 1B | S1-4 | Select between Max10 CPLD JTAG ('high', ON) or JTAG forwarding to SoM ('low', OFF). |
TCK | in | G2 | down (external) | 3.3 V | 1B | U8-12 | JTAG from FTDI to MAX10 |
TMS | in | G1 | up (external) | 3.3 V | 1B | U8-15 | |
TDO | out | F6 | 3.3 V | 1B | U8-14 | ||
TDI | in | F5 | up (external) | 3.3 V | 1B | U8-13 | |
DIP1 | in | G4 | up (external) | 3.3 V | 1B | S1-1 | User Dip |
EN_C5VIN | out | F4 | down (external) | 3.3 V | 1B | Q2-5 | Enable 5V on CRUVI connectors (C5VIN rail). |
CB_SMB_SCL | H3 | 3.3 V | 1B | J11-7 | CRUVI CB HS, currently not used | ||
CB_SMB_ALERT | H2 | 3.3 V | 1B | J11-3 | CRUVI CB HS, currently not used | ||
LED5 | out | H6 | 3.3 V | 2 | D5 | User LED | |
CB_SMB_SDA | G5 | 3.3 V | 2 | J11-5 | CRUVI CB HS, currently not used | ||
CB_DI | J2 | 3.3 V | 2 | J11-51 | CRUVI CB HS, currently not used | ||
CB_REFCLK | J1 | 3.3 V | 2 | J11-11 | CRUVI CB HS, currently not used | ||
OSCI_CPLD | H4 | 3.3 V | 2 | U7-3 | currently not used | ||
CB_MODE | M2 | 3.3 V | 2 | J11-57 | CRUVI CB HS, currently not used | ||
CB_DO | M1 | 3.3 V | 2 | J11-53 | CRUVI CB HS, currently not used | ||
CA_DO | N3 | 3.3 V | 2 | J10-53 | CRUVI CA HS, currently not used | ||
CA_SCK | N2 | 3.3 V | 2 | J10-59 | CRUVI CA HS, currently not used | ||
CA_MODE | L3 | 3.3 V | 2 | J10-57 | CRUVI CA HS, currently not used | ||
CA_SEL | M3 | 3.3 V | 2 | J10-55 | CRUVI CA HS, currently not used | ||
CB_SEL | K2 | 3.3 V | 2 | J11-55 | CRUVI CB HS, currently not used | ||
DIP2 | in | K1 | 3.3 V | 2 | S1-3 | IOV voltage selection (firmware dependent)/User Dip | |
CB_SCK | L2 | 3.3 V | 2 | J11-59 | CRUVI CB HS, currently not used | ||
DIP3 | in | L1 | up (external) | 3.3 V | 2 | S1-5 | SoM CPLD selection (firmware dependent)/User Dip |
LED8 | out | L4 | 3.3 V | 3 | D8 | System status LED (firmware dependent)/User LED | |
BUTTON1 | in | L5 | down (external) | 3.3 V | 3 | S3 | User Button |
CA_SMB_SCL | M5 | 3.3 V | 3 | J10-7 | CRUVI CA HS, currently not used | ||
CA_SMB_SDA | M4 | 3.3 V | 3 | J10-5 | CRUVI CA HS, currently not used | ||
LED7 | out | K5 | 3.3 V | 3 | D7 | Power status LED (firmware dependent)/User LED | |
CA_SMB_ALERT | N5 | 3.3 V | 3 | J10-3 | CRUVI CA HS, currently not used | ||
CA_DI | N4 | 3.3 V | 3 | J10-51 | CRUVI CA HS, currently not used | ||
CA_REFCLK | N6 | 3.3 V | 3 | J10-11 | CRUVI CA HS, currently not used | ||
VS1 | out | N8 | up (external) | 3.3 V | 3 | U3-18 | IOV voltage selection pin |
ETH_LED1 | out | K6 | 3.3 V | 3 | J2B | Integrated Ethernet Jack LED, currently tied to GND. Using as ETH status depends on attached SoM and is therefore not implemented. | |
LED4 | out | J6 | 3.3 V | 3 | D4 | User LED | |
EN_C3_3V | out | M9 | down (external) | 3.3 V | 3 | Q1-5 | Enable 5V on CRUVI connectors (C5VIN rail). |
VS2 | out | M8 | down (external) | 3.3 V | 3 | U3-17 | IOV voltage selection pin |
PGOOD | in | J7 | 3.3 V | 3 | JB1-29 | SoM power good signal | |
F_UART_TX | in | M12 | 3.3 V | 3 | U8-32 | UART TX connected to FTDI | |
SD_CD | in | M13 | 3.3 V | 3 | J8-9 | ||
VS0 | out | N9 | down (external) | 3.3 V | 3 | U3-19 | IOV voltage selection pin |
EN_IOV | out | N10 | down (external) | 3.3 V | 3 | Q1-5 | Enable 5V on CRUVI connectors (C5VIN rail). |
ETH_LED2 | out | L11 | 3.3 V | 3 | J2C | Integrated Ethernet Jack LED, currently tied to GND. Using as ETH status depends on attached SoM and is therefore not implemented. | |
USB_OC | in | M11 | up (external) | 3.3 V | 3 | U5-5 | USB over current alert pin ('low' when overcurrent is detected) |
EN1 | out | K8 | 3.3 V | 3 | JB1-27 | SoM enable control pin (depnds on attached SoM) | |
MODE | out | J8 | 3.3 V | 3 | JB1-31 | SoM Mode control pin (depnds on attached SoM) | |
RESIN | out | L10 | 3.3 V | 3 | JB2-17 | SoM reset input | |
F_UART_RX | out | M10 | 3.3 V | 3 | U8-33 | UART RX, connected to FTDI | |
M3_3VOUT | in | N12 | down (external) | 3.3 V | 3 | JB2-9 | SoM 3.3V, used as SoM power good |
M_TDO | in | J10 | VCCJTAG | 5 | JB2-98 | SoM JTAG | |
M_TMS | out | L12 | VCCJTAG | 5 | JB2-94 | ||
M_TCK | out | H8 | VCCJTAG | 5 | JB2-100 | ||
M_TDI | out | L13 | VCCJTAG | 5 | JB2-96 | ||
M_G1_20 | out | G9 | VCCIO_CC | 6 | JB1-32 | SoM signal to/from CPLD | |
M_G1_02 | in | G10 | VCCIO_CC | 6 | JB1-35 | SoM signal to/from CPLD | |
M_G1_05 | out | F13 | VCCIO_CC | 6 | JB1-45 | SoM signal to/from CPLD | |
M_G1_07 | out | E13 | VCCIO_CC | 6 | JB1-49 | SoM signal to/from CPLD | |
M_G1_06 | out | F12 | VCCIO_CC | 6 | JB1-47 | SoM signal to/from CPLD | |
M_G1_08 | out | E12 | VCCIO_CC | 6 | JB1-51 | SoM signal to/from CPLD | |
M_G1_01 | in | F9 | VCCIO_CC | 6 | JB1-37 | SoM signal to/from CPLD | |
M_G1_04 | in | F10 | VCCIO_CC | 6 | JB1-41 | SoM signal to/from CPLD | |
M_G1_15 | E9 | VCCIO_CC | 6 | JB1-34 | SoM signal to/from CPLD, currently not used | ||
M_G1_13 | B12 | VCCIO_CC | 6 | JB1-65 | SoM signal to/from CPLD, currently not used | ||
M_G1_18 | in | B11 | VCCIO_CC | 6 | JB1-42 | SoM signal to/from CPLD | |
M_G1_11 | C12 | VCCIO_CC | 6 | JB1-59 | SoM signal to/from CPLD, currently not used | ||
M_G1_17 | in | C11 | VCCIO_CC | 6 | JB1-44 | SoM signal to/from CPLD | |
M_G1_12 | B13 | VCCIO_CC | 6 | JB1-61 | SoM signal to/from CPLD, currently not used | ||
M_G1_14 | A12 | VCCIO_CC | 6 | JB1-67 | SoM signal to/from CPLD, currently not used | ||
M_G1_19 | in | E10 | VCCIO_CC | 6 | JB1-39 | SoM signal to/from CPLD | |
M_G1_16 | out | D9 | VCCIO_CC | 6 | JB1-38 | SoM signal to/from CPLD | |
M_G1_09 | D12 | VCCIO_CC | 6 | JB1-55 | SoM signal to/from CPLD, currently not used | ||
M_G1_03 | in | D11 | VCCIO_CC | 6 | JB1-36 | SoM signal to/from CPLD | |
M_G1_10 | C13 | VCCIO_CC | 6 | JB1-57 | SoM signal to/from CPLD, currently not used | ||
LED3 | out | C10 | 3.3 V | 8 | D3 | User LED | |
NOSEQ | out | C9 | 3.3 V | 8 | JB1-8 | SoM control pin for power sequenzing (SoM dependent) | |
M_G6_07 | in | A8 | 3.3 V | 8 | JB1-98 | SoM signal to/from CPLD | |
PROGMODE | out | A9 | 3.3 V | 8 | JB1-90 | ||
M_G6_06 | B10 | (pullup not fitted) | 3.3 V | 8 | JB1-96 | SoM signal to/from CPLD, currently not used, | |
M_G6_05 | B9 | (pullup not fitted) | 3.3 V | 8 | JB1-94 | SoM signal to/from CPLD, currently not used | |
M_G6_04 | in | A10 | 3.3 V | 8 | JB1-92 | SoM signal to/from CPLD | |
M_G6_03 | A11 | 3.3 V | 8 | JB1-88 | SoM signal to/from CPLD, currently not used | ||
LED2 | out | D8 | 3.3 V | 8 | D2 | User LED | |
LED1 | out | E8 | 3.3 V | 8 | D1 | User LED | |
M_G6_08 | in | A7 | 3.3 V | 8 | JB1-100 | SoM signal to/from CPLD | |
CC_SMB_ALERT | A6 | 3.3 V | 8 | J12-3 | CRUVI CC HS, currently not used | ||
M_G6_02 | in | B6 | 3.3 V | 8 | JB1-86 | SoM signal to/from CPLD | |
CC_REFCLK | B5 | 3.3 V | 8 | J12-11 | CRUVI CC HS, currently not used | ||
CC_SMB_SDA | A4 | 3.3 V | 8 | J12-5 | CRUVI CC HS, currently not used | ||
CC_SMB_SEL | A3 | 3.3 V | 8 | J12-55 | CRUVI CC HS, currently not used | ||
M_G6_01 | out | D6 | 3.3 V | 8 | JB1-91 | SoM signal to/from CPLD | |
CC_SCK | B3 | 3.3 V | 8 | J12-59 | CRUVI CC HS, currently not used | ||
CC_DI | B4 | 3.3 V | 8 | J12-51 | CRUVI CC HS, currently not used | ||
CC_DO | A2 | 3.3 V | 8 | J12-53 | CRUVI CC HS, currently not used | ||
CC_MODE | B3 | 3.3 V | 8 | J12-57 | CRUVI CC HS, currently not used | ||
CC_SMB_SCL | A5 | 3.3 V | 8 | J12-7 | CRUVI CC HS, currently not used | ||
LED6 | out | B7 | 3.3 V | 8 | D6 | User LED | |
BUTTON0 | in | E7 | up (external) | 3.3 V | 8 | S2 | SoM reset button/User button |
Level shifting/MUX
In this Firmware Version CRUVI Low Speed connector CA has four signals configured as input and another four as output. Depending on the connectors and signals used/needed this can be changed by customizing and updateing the firmware. Also the 3.3V signals on the three CRUVI High Speed connectors can be utilized in that way.
X0 <= M_G1_01 ;
X2 <= M_G1_02 ;
X4 <= M_G1_03 ;
X6 <= M_G1_04 ;
M_G1_05 <= X1;
M_G1_06 <= X3;
M_G1_07 <= X5;
M_G1_08 <= X7;
JTAG/ UART forward to 4x5 module
JTAG
Switch with hard wired JTAGEN Dip4 between user mode of pins, which corresponds due to the lines below to SoM JTAG ("OFF", open, 'low') and Max10 CPLD ("ON", closed, 'high')
TDO <= M_TDO;
M_TMS <= TMS;
M_TCK <= TCK;
M_TDI <= TDI;
UART
M_G6_01 <= F_UART_TX; --TX UART to SoM
F_UART_RX <= M_G6_02; --RX UART from SoM
Module control pins
RESIN <= BUTTON0; -- reset SoM
NOSEQ <= net_gnd; -- powermanagement by CPLD is NOT disabled
PROGMODE <= not(DIP3); -- select between CPLD (low, closed, on) on SoM or FPGA/SoC (high, open, off )
EN1 <= net_vcc; --module power always enabled
MODE <= SD_CD ; -- select SD boot mode when card installed ('low'), else QSPI ('high')
Button and Dips
User Button
User button on PL is debounced:
M_G1_20 <= Button1_db;
User Dips:
Dip1 is directly forwarded to a PL IO:
M_G1_16 <= not(DIP1);
Dip2 is used for IO Voltage selection, see IO Voltage selection
Dip3 is used for JTAG selection, see Module control pins
LEDs
Status LEDs
The LED D7 and D8 are utilized for board status and power information in the following way:
Sequenz | Description D7 (red) | Description D8 (green) | |
---|---|---|---|
OFF | LED OFF | Power OK | currently not used |
*ooooooo | 1 times blinking with a break | SoM Power error (PGOOD 'low' or M3_3VOUT 'low') | currently not used |
**oooooo to ****oo | 2, 3, 4 times blinking with a break | currently not used | currently not used |
*****ooo | 5 times blinking with a break | USB power errror (USB_OC 'low) | SoM CPLD JTAG enabled |
******oo to ******** | 6, 7, 8 times blinking with a break | currently not used | currently not used |
ON | LED ON | currently not used | System OK |
USR LEDs
User LEDs D1, D2, D3 (green) are connected to PL IOs:
LED3 <= M_G1_19;
LED2 <= M_G1_18;
LED1 <= M_G1_17;
User LEDs D4, D5, D6 (red) are connected to IOs which are located at PL or PS depending on SoM.
LED4 <= M_G6_04;
LED5 <= M_G6_07;
LED6 <= M_G6_08;
ETH LEDs
Ethernet Jack LEDs are not used in this firmware and are therefore tied to GND.
ETH_LED2 <= net_gnd;
ETH_LED1 <= net_gnd;
Power sequenzing
The M3.3VOUT signal of the SoM is used to Enable CRUVI power rails and the SOM IO Voltage:
EN_C5VIN <= M3_3VOUT;
EN_C3_3V <= M3_3VOUT;
EN_IOV <= M3_3VOUT;
IO Voltage selection
Select IOV Voltage of DCDC U3:
VS0 <= not(DIP2);
VS1 <= DIP2;
VS2 <= net_gnd;
"010" selects 1.8V (Dip2 open, "OFF", 'high').
"001" selects 2.5V (Dip2 closed, "ON", 'low').
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Revision Changes
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
REV01 | REV01, REV02 | initial version | |||
All |
Legal Notices
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