TE0835 Getting Started

TEB0835 with TE0835

Overview

Board Overview

Power supply

Single 12V power supply with minimum current capability of 3A is recommended to power on the board.

DIP-Switches and Push Buttons

There is a push button RST which is connected to RESET signal, it resets the system entirely.

Signal	Designator	Connected to	Active Level	Description
RST	BTN1	B2B JB1 pin 36	Active low	Reset push button

S2-A	S2-B	S2-C	S2-D	Description
CPLD_IO0	CPLD_IO1	CPLD_IO2	JTAGEN	CPLD_IO0 and CPLD_IO1 for boot mode selection CPLD_IO2 is used as FPGA IO. JTAGEN is used to program the CPLD of the TE0835 module.

CPLD_IO1 (S2-B)	CPLD_IO0 (S2-A)	Boot Mode	Description
0 (ON)	0 (ON)	JTAG Mode
0 (ON)	1 (OFF)	QSPI Mode
1 (OFF)	0 (ON)	----	Undefined
1 (OFF)	1 (OFF)	SD Card Mode

Dip Switch S1	Signal	Status	Description
S2-D	JTAGEN	ON	Module FPGA JTAG access
S2-D	JTAGEN	OFF	Module CPLD JTAG access

DIP Switches /Push Buttons

Jumpers

Designator

Pins

Default set to

Description

J39

MODULE_PG

DCDC_EN

PG_5V

MODULE_PG and DCDC_EN

If the jumper set to MODULE_PG the enable signal of 3.3V DC-DC regulator on the carrier board will be controlled via the power good signal of the TE0835 module.

Jumpers

LEDs

There are three user LEDs which can be used for variant purposes.

Designator	Color	Connected to	Active Level	Note
D1	Green	PWR_STATUS	Active high	Shows the various states of the power on the module. The user can determine the type of occured error on the module.
D2	Red	DBG_LED0 → AJ18 of the FPGA	Active low	Debug LED
D3	Red	DBG_LED1 → AH18 of the FPGA	Active low	Debug LED
D4	Red	DBG_LED2 → AF18 of the FPGA	Active low	Debug LED
D5	Red	DBG_LED3 → AD18 of the FPGA	Active low	Debug LED

LED D1 States	Blink Sequence	Description
IDLE	ooooooooooooooooooo*	Power Sequencing can not start. RESETN is active.
pg_all = '0'	oooooooooooo	An unknown error has occurred. The power supply must be switched off.
Stage 1	oooooooooooooooooo	The correct voltage in one of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC
Stage 2	ooooooooooooooooo*	The correct voltage in one of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT
Stage 3	oooooooooooooooo	The correct voltage in one of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2
Stage 4	ooooooooooooooo*	The correct voltage in one of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3
Stage 5	oooooooooooooo	The correct voltage in one of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT
USR (RDY and DONE='1')	User defined	Power is ok and the FPGA is configured successfully. LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high)
WAIT_RDY / RDY and DONE='0'	ooooooooooooo*	Power is ok. But the FPGA is not yet configured.

The period for erery blink (*o) is 0.5sec.

Module LEDs

Designator	Color	Connected to	Active Level	Note
D1	Green	PG_1V8	Active high	If this LED is ON , the output voltage of the 1.8V regulator U1 is correct.
D2	Green	PG_3.3V	Active high	If this LED is ON , the output voltage of the 3.3V regulator U4 is correct.
D3	Green	PG_5V	Active high	If this LED is ON , the output voltage of the 5V regulator U8 is correct.
D6	Green	B49_L5_P → B2B J18 Pin 122	Active high	User LED
D7	Green	B49_L5_N → B2B J18 Pin 124	Active high	User LED
D8	Green	B49_L6_P → B2B J18 Pin 126	Active high	User LED
D9	Green	B49_L6_N → B2B J18 Pin 128	Active high	User LED
D10	Green	B49_L7_P → B2B J18 Pin 130	Active high	User LED
D11	Green	B49_L7_N → B2B J18 Pin 132	Active high	User LED
J31B	Green / Yellow	PHY_LED0 → B2B J17 Pin 50	Active low / Active high	Connected to the LED0 pin of the Ethernet PHY chip on the module TE0835
J31C	Green / Yellow	PHY_LED1 → B2B J17 Pin 52	Active low / Active high	Connected to the LED1 pin of the Ethernet PHY chip on the module TE0835

Carrier LEDs

JTAG/UART

JTAG and UART connections are available through micro USB connector.

UART0
Designator J29
FTDI Chip UART Pins	Connected to	B2B Pin on the carrier	B2B Pin on the module	Connected to	Direction in FPGA	Description
BDBUS0	UART0_RX	B2B J17 Pin 43	B2B J1 Pin 43	FPGA MIO42 Pin E20	IN	UART0 RXD
BDBUS1	UART0_TX	B2B J17 Pin 45	B2B J1 Pin 45	FPGA MIO43 Pin A19	OUT	UART0 TXD

UART1
UART Pins	CPLD Chip Pins	Connected to	Direction in FPGA	Description
UART1_TXD	29	FPGA MIO28 Pin J19	IN	Unused in the current firmware REV01
UART1_RXD	28	FPGA MIO29 Pin H21	OUT	Unused in the current firmware REV01

JTAG
Designator J29
FTDI Chip JTAG Pins	Connected to	B2B Pin on the carrier	B2B Pin on the module	Connected to	In firmware forwarded to	Connected to	Direction in FPGA	Description
ADBUS0	JTAG_TCK	B2B J17 Pin 22	B2B J1 Pin 22	CPLD Chip U31 Pin 45	CPLD Chip U31 Pin 10	FPGA Pin P26	IN	Test Clock
ADBUS1	JTAG_TDI	B2B J17 Pin 20	B2B J1 Pin 20	CPLD Chip U31 Pin 47	CPLD Chip U31 Pin 8	FPGA Pin M26	IN	Test Data Input
ADBUS2	JTAG_TDO	B2B J17 Pin 18	B2B J1 Pin 18	CPLD Chip U31 Pin 48	CPLD Chip U31 Pin 11	FPGA Pin T26	OUT	Test Data Output
ADBUS3	JTAG_TMS	B2B J17 Pin 24	B2B J1 Pin 24	CPLD Chip U31 Pin 44	CPLD Chip U31 Pin 9	FPGA Pin N25	IN	Test Mode Select

JTAG / UART

I2C

I2C Pins	Signal / CPLD Chip Pins	Connected to	Description
SDA	FPGA_IO1 / 26	FPGA Pin AE16	Unused in the current firmware version REV01
SCL	FPGA_IO0 / 27	FPGA Pin AE18	Unused in the current firmware version REV01

I2C

ADC / DAC Port

There are 8 ADCs and 8 DACs on the TE0835 module as shown:

RF Analyzer GUI	Board TE0835 ( RFSoC U1)			TEB0835
Tile /Converter	SoC Pin Name	SoC Pin Number	B2B	Signal Name	Connector Designator	Connector Type
ADC Tile 0-ADC 01	ADC0_P/ADC0_N	AK2/AK1	31/29	ADC0_P/ADC0_N	J1	SMA
ADC Tile 0-ADC 23	ADC1_P/ADC1_N	AH2/AH1	43/41	ADC1_P/ADC1_N	J2	UFL
ADC Tile 1-ADC 01	ADC2_P/ADC2_N	AF2/AF1	49/47	ADC2_P/ADC2_N	J3	SMA
ADC Tile 1-ADC 23	ADC3_P/ADC3_N	AD2/AD1	59/61	ADC3_P/ADC3_N	J4	UFL
ADC Tile 2-ADC 01	ADC4_P/ADC4_N	AB2/AB1	67/65	ADC4_P/ADC4_N	J5	SMA
ADC Tile 2-ADC 23	ADC5_P/ADC5_N	Y2/Y1	79/77	ADC5_P/ADC5_N	J6	UFL
ADC Tile 3-ADC 01	ADC6_P/ADC6_N	V2/V1	85/83	ADC6_P/ADC6_N	J7	SMA
ADC Tile 3-ADC 23	ADC7_P/ADC7_N	T2/T1	97/95	ADC7_P/ADC7_N	J8	UFL
DAC Tile 0-DAC 0	DAC0_P/DAC0_N	N2/N1	103/101	DAC0_P/DAC0_N	J9	SMA
DAC Tile 0-DAC 1	DAC1_P/DAC1_N	L2/L1	109/107	DAC1_P/DAC1_N	J10	UFL
DAC Tile 0-DAC 2	DAC2_P/DAC2_N	J2/J1	121/119	DAC2_P/DAC2_N	J11	SMA
DAC Tile 0-DAC 3	DAC3_P/DAC3_N	G2/G1	127/125	DAC3_P/DAC3_N	J12	UFL
DAC Tile 1-DAC 0	DAC4_P/DAC4_N	E2/E1	133/131	DAC4_P/DAC4_N	J13	UFL
DAC Tile 1-DAC 1	DAC5_P/DAC5_N	C2/C1	139/137	DAC5_P/DAC5_N	J14	UFL
DAC Tile 1-DAC 2	DAC6_P/DAC6_N	B4/A4	151/149	DAC6_P/DAC6_N	J15	UFL
DAC Tile 1-DAC 3	DAC7_P/DAC7_N	B6/A6	157/155	DAC7_P/DAC7_N	J16	UFL

RF Analyzer GUI	Board TE0835 ( RFSoC U1)			TEB0835
Tile /Converter	SoC Pin Name	SoC Pin Number	B2B	Signal Name	Connector Designator	Connector Type
ADC Tile 0-ADC 01	ADC0_P/ADC0_N	AK2/AK1	31/29	ADC0_P/ADC0_N	J1	SMA
ADC Tile 0-ADC 23	ADC1_P/ADC1_N	AH2/AH1	43/41	ADC1_P/ADC1_N	J2	UFL
ADC Tile 1-ADC 01	ADC2_P/ADC2_N	AF2/AF1	49/47	ADC2_P/ADC2_N	J3	SMA
ADC Tile 1-ADC 23	ADC3_P/ADC3_N	AD2/AD1	59/61	ADC3_P/ADC3_N	J4	UFL
ADC Tile 2-ADC 01	ADC4_P/ADC4_N	AB2/AB1	67/65	ADC4_P/ADC4_N	J5	SMA
ADC Tile 2-ADC 23	ADC5_P/ADC5_N	Y2/Y1	79/77	ADC5_P/ADC5_N	J6	UFL
ADC Tile 3-ADC 01	ADC6_P/ADC6_N	V2/V1	85/83	ADC6_P/ADC6_N	J7	SMA
ADC Tile 3-ADC 23	ADC7_P/ADC7_N	T2/T1	97/95	ADC7_P/ADC7_N	J8	UFL
DAC Tile 0-DAC 0	DAC0_P/DAC0_N	N2/N1	103/101	DAC0_P/DAC0_N	J9	SMA
DAC Tile 0-DAC 2	DAC1_P/DAC1_N	L2/L1	109/107	DAC1_P/DAC1_N	J10	UFL
DAC Tile 1-DAC 0	DAC2_P/DAC2_N	J2/J1	121/119	DAC2_P/DAC2_N	J11	SMA
DAC Tile 1-DAC 2	DAC3_P/DAC3_N	G2/G1	127/125	DAC3_P/DAC3_N	J12	UFL
DAC Tile 2-DAC 0	DAC4_P/DAC4_N	E2/E1	133/131	DAC4_P/DAC4_N	J13	UFL
DAC Tile 2-DAC 2	DAC5_P/DAC5_N	C2/C1	139/137	DAC5_P/DAC5_N	J14	UFL
DAC Tile 3-DAC 0	DAC6_P/DAC6_N	B4/A4	151/149	DAC6_P/DAC6_N	J15	UFL
DAC Tile 1-DAC 2	DAC7_P/DAC7_N	B6/A6	157/155	DAC7_P/DAC7_N	J16	UFL

Reference Designs

TE0835 Reference Designs

Trenz Electronic Documentation