- Created by Mohsen Chamanbaz, last modified on 01 09, 2023
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Overview
Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
Key Features
- Libero SoC v2023.1
- SoftConsole v2022.2-RISC-V-747
- PolarfireSoC MSS Configurator v2023.1
- HSS (Hardware System Service) v2023.02
- Microchip polarfire SoC BSP v2022.11
- Yocto Kirkstone
- UART
- ETH
- USB
- I2C
- QSPI flash
- DDR3 memory
- User LED
Revision History
Date | Libero SoC | Project Built | Authors | Description |
---|---|---|---|---|
2023-08-24 | v2023.1 | ????? | Mohsen Chamanbaz |
|
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Requirements
Software
Software | Version | Note |
---|---|---|
Libero SoC | v20223.1 | needed |
SoftConsole | v2022.2 | needed |
PolarfireSoC MSS Configurator | v2023.1 | needed |
Yocto | Kirkstone | needed |
Additional software requirement
Requirement | Version | Note |
---|---|---|
hart software services | v2023.02 | needed |
Microchip BSP for polarfire SoC (meta-polarfire-soc-yocto-bsp) | v2022.11 | needed |
Hardware
Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | Yocto Machine Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|---|
TEM0007-01-S002* | 25_1E0_ES_1GB | tem0007 | REV01 | 1GB | 64MB | ---- | ---- | ---- |
TEM0007-01-CHE11-A | 250_1E_1GB | tem0007 | REV01 | 1GB | 64MB | ---- | ---- | ---- |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
Modified TE0703* | As carrier board. This board must be modified. For more information see Modified TE0703 for Microchip Getting Started |
*used as reference
Additional HW Requirements:
Additional Hardware | Quantity | Notes |
---|---|---|
TE0790 XMOD | 1 | For HSS console |
Mini USB cable for JTAG/UART | 2 | Check Carrier Board and Programmer for correct type |
RJ45 Ethernet cable | 1 | |
SD card | 1 | At least 8GB |
USB Stick | 1 | Optional |
Content
For general structure and usage of the reference design, see Project Delivery - Microchip devices
Design Sources
Type | Location | Notes |
---|---|---|
Libero | <project folder>/libero_source <project folder>/test_board_<Board Part Short Name> | Libero project will be generated by TE Scripts (Optional) Source files for specific assembly variants |
SoftConsole | <project folder>/softconsole_source | Additional software will be generated by TE Scripts |
Yocto | <project folder>/os/yocto | Yocto BSP layer template for linux |
Prebuilt
File | File-Extension | Description |
---|---|---|
Libero Project File | *.prjx | Project file |
FlashPro Express Job | *.job | Programming file |
Constraint File | *.pdc | IO constraint file |
Timing Constraint File | *.sdc | Timing constraint file |
Components in Block Design | *.cxf | Exported file of polarfire MSS configuration software for importing in Libero |
Configuration File | *.cfg | Polarfire MSS configuration file |
Software-Application-File | *.hex | Generated hex file by SoftConsole software to program on eNVM memory of Polarfire SoC |
Software-Application-File | *.elf | Software application for SoftConsole |
Device Tree | *.dtb | Device tree blob |
CONF-File | *.conf | Boot configuration file (extlinux.conf) |
Yocto linux image | *.wic | This File can be flashed via bmaptool on the SD card. |
Yocto linux image | *.img | Linux image for SD card |
Download
Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.
Reference design is available on:
Design Flow
Libero SoC
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Libero Design Flow.
See also:
The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.
The "normal" Libero project will be generated in the subfolder "/Libero-<Variant short name>/".
To create project do the following steps:
- Execute "Generate_TEM0007_Hardware-Design_in_Libero_SoC_v2023.1.cmd"
- Choose one of the following options::
- Press 0 , if the path of installed libero software is : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe
- Press 1, if it will be entered the path Microchip or Libero SoC installations folder. The script selects automatically the Libero exe.
- Press 2, if it will be entered the full path to the Libero SoC exe.
- Press 3 to exit the script.
- Press 0 , if the path of installed libero software is : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe
- Select your board in "Board selection" , if there is more than one variant.
- Choose one of the following options for prefered hardware description language:
- Option 0 : VHDL
- Option 1 : VERILOG
- Option 2 : To exit th script
- If the suggested name for the project is acceptable enter y or t or 1. Otherwise enter n or f or 0 and enter the desired name.
- Project will be generated automatically.
- Open the generated project by entering y or t or 1Example
- After opening Libero project double click on Generate Bitstream menu in Design Flow box to generate the bitstream file.
- After generating bit stream file double click on Configure Design Initialization Data and Memories in Design Flow bow. It will be opened a window.
- Click on eNVM and after that on Add and click on Add Boot Mode 1 Client.
- Enter the path of generated *.hex File by SoftConsole software (HSS) and click on OK.
- Save the project and double click on Generate Bitstream again.
- Double click on Flashpro Express to generate *.job File
Hart Software Services (HSS)
This is Hart Software Services (HSS) code.On PolarFire SoC, this is comprised of two portions:
A superloop monitor running on the E51 minion processor, which receives requests from the individual U54 application processors to perform certain services on their behalf;
A Machine-Mode software interrupt trap handler, which allows the E51 to send messages to the U54s, and request them to perform certain functions for it related to rebooting a U54.
The HSS performs boot and system monitoring functions for PolarFire SoC. The HSS is compressed (DEFLATE) and stored in eNVM. On power-up, a small decompressor wrapper inflates the HSS from eNVM flash to L2-Scratchpad memory and starts the HSS.
Creating HSS workspace in SoftConsole
- Download the test board design zip file in the following path : TEM0007 "Test Board" Reference Design
- Unzip the test board zip file
- Copy the HSS folder (hart-software-services-<HSS version>) from softconsole_source folder in the SoftConsole workspace folder
- Open SoftConsole software as administrator
- Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-<HSS version> folder.
- Left click on board folder
- There is created already a subfolder for TEM0007 module and HSS is ready to be compiled as shown:
- Right click on hart-software-services-<HSS version> and click on Build project to compile it.
- It is ready to program created hex file on the Polarfire SoC. See Programming
Note that HSS can be changed for every TEM0007 variant. Therefore the hex file for every variant is created and saved in the following path of test design folder separately: (prebuilt/soctware/<short name of the module variant>)
Creating XML file in PolarfireSoC MSS Configurator Software
To create HSS file for a desired module variant the saved MSS configuration xml file in soc_fpgs_design/xml/ folder must be matched for its related xml file. To do it:
- Open the PolarfireSoC MSS Configurator software.
- Click on Project→Open
- Select the generated TEM0007_MSS.cfg file that is saved in the libero_source/mss folder while creating the Libero design.
- Click on Generate icon. It will be opened a window to enter the desired path for generated xml file.
- MSS configuration xml file is generated. This file must be imported in SoftConsole software. To import this file copy the generated MSS configuration xml file and replace it with previous xml file in the following path ( <softconsole workspace folder>/ hart-software-services-<HSS version>/boards/TEM0007/soc_fpga_design/xml ).
- In SoftConsole software click on Project/Clean.
- In SoftConsole software delete all configuration header files in hart-software-services-<HSS version>/boards/TEM0007/fpga_design-config folder.
- In SoftConsole software compile HSS again by clicking on Project/Build Project.
- The new configuration header files will be generated again by the python script in hart-software-services-<HSS version>/tools/polarfire-soc-configuration-generator/mpfs_configuration_generator.py folder. The generated hex file can be found in the hart-software-services-<HSS version>/Default folder.
- This new hex file must be replaced in Libero to generate new Bitstream file, if this hex file should be attached in Bitstream file. See Libero SoC
Note that this hex file can be programmed in eNVM in SoftConsole directly. See Programming eNVM in SoftConsole
Launch
Hardware Setup
see Modified TE0703 for Microchip Getting Started
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Programming eNVM
The eNVM is a user non-volatile flash memory that can be programmed independently. There is two methods to program eNVM:
Programming eNVM in SoftConsole
To program HSS *.elf file on FPGA:
- Prepare the hardware see Hardware Setup
- Open SoftConsole software as administrator, if it is not done yet.
- Select correct directory as workspace directory.
- Build the hart-software-services-master , if it is not done yet.
- Click on Run > External Tools > Polarfire SoC program non-secure boot-mode 1
Programming eNVM in Flashpro Express
The HSS generated hex file can be attached to bitstream file. For more information see Design Flow
To program the eNVM in Flashpro Express see Using FlashPro Express
Programming Bitstream
There is two ways to program bitstream file on FPGA:
Using Libero SoC
- Connect the TEM0703 board via its Mini-USB connector. (J4)
- After generating bitstream in Libero click on Run PROGRAM Action to program bitstream file on FPGA.
Using FPExpress software
- Connect the board via USB connector
- Export *.job file , if does not exist yet.
- Click on new
- Give path of job file by clicking on Browse
- Click on OK
- Click on RUN
Get prebuilt boot binaries
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Run create_project_win.cmd/create_project_linux.shSelect Module in 'Board selection'Click on 'Export prebuilt files' buttonFolder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened
SD-Boot mode
This module supports SD card boot mode. There is no dip switch to select boot mode. The selection between SD card or other boot mode will be done in HSS. TEM0007 module supports SD card boot mode and JTAG boot mode.
Prepare SD card as follows for SD card boot mode:
- Extract SD_Card.zip file
- Now there is a image file (SD_Card.img)
- Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.
- In the case of writing image file in linux there are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:
- Insert SD card in the SD card reader
bmaptool copy --nobmap <Path of image file *.img> /dev/sdX
- After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
dd if=<Path of image file *.img> of=/dev/sdX
- After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Hardware Setup
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
- Open two serial console for HSS and Linux console (e.g. PuTTY)
Select COM Port of linux console (UART1)
Win OS: see device manager
Linux OS: see dmesg | grep tty (UART is *USB1)
- Select COM port if HSS console (UART0)
- Speed for both consoles : 115200
- Press reset button
- Console output depends on used Software project, see Application
- Linux Console (UART1):
Login data:
Note: Wait until Linux boot finished
tem0007 login: root
You can use Linux shell now.
i2cdetect -l (check I2C Bus) ifconfig -a (ETH0 check) lsusb (USB check)
- HSS console (UART0):
- This console can be monitored by user , to know some additional information same as SD card status ( If SD card by booting is detected or not) , U54 cores status or memory size , ....
- This console can be monitored by user , to know some additional information same as SD card status ( If SD card by booting is detected or not) , U54 cores status or memory size , ....
System Design - Libero
Block Design
The block designs may differ depending on the assembly variant.
HPS Interfaces
Activated interfaces:
Type | Note |
DDR | -- |
EMAC0 | -- |
EMAC1 | -- |
GPIO0 | -- |
GPIO1 | -- |
GPIO2 | -- |
I2C0 | -- |
I2C1 | -- |
QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB0 | -- |
USB1 | -- |
Software Design - SoftConsole
Application
Template location: <project folder>/softconsole_source/
Creating new HSS workspace in SoftConsole for neu module variant
- Download the HSS folder here: hart-software-services
- Unzip the hart-software-services-2023.02 zip file in the SoftConsole workspace
- Open SoftConsole software as administrator
- Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-2023.02 folder
- Right click on board folder in the left side and click on new folder
- Rename the folder for desired board. For example for TEM0007 module rename it to TEM0007. If there is TEM0007, this HSS workspace was created already and HSS is ready to be compiled.
- Create other subfolders as shown (For example for TEM0007):
- hart-software-serevices-2023.02
- board
- TEM0007
- drivers_config
- fpga_ip
- miv_ihc
- Copy miv_ihc_add_mapping.h and miv_ihc_config.h files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder.
- miv_ihc
- fpga_ip
- fpga_design_config
- This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
- This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
- mpfs_hal_config
- Copy mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
- Copy mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
- soc_fpga_design
- xml
- Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
- Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
- xml
- Copy the following files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder (TEM0007 folder) :
- hss_board_init.c
- Edit the following line to avoid using USB interface without DMA. If this line don't be commented, DMA option for USB interface in linux kernel must be deactivated for USB interface to operate USB interface correctly.
- Edit the following line to avoid using USB interface without DMA. If this line don't be commented, DMA option for USB interface in linux kernel must be deactivated for USB interface to operate USB interface correctly.
- hss_usrt_init.c
- usrt_helper.c
- hss_I2Scratch.lds
- Kconfig
- Edit Kconfig for example for TEM0007 module as shown:Kconfig
menu "TEM0007 Design Configuration Options" config SOC_FPGA_DESIGN_XML string "Enter path to Libero XML file" default "boards/$(BOARD)/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml" help This option specifies the design XML file to use. endmenu
- Edit Kconfig for example for TEM0007 module as shown:
- hss_board_init.c
- drivers_config
- TEM0007
- board
- hart-software-serevices-2023.02
- Makefile
- Edit Makefile for example for TEM0007 module as shown:Makefile of TEM0007 folder
- Edit Makefile for example for TEM0007 module as shown:
- Makefile
- To operate SD card correctly edit the file in the following path: ....\hart-software-services-2023.02\baremetal\polarfire-soc-bare-metal-library\src\platform\drivers\mss\mss_mmc\mss_mmc.c . For last version of hart-software-sevices (Version 2023.06) this bug is fixed. For more information refer to : https://github.com/polarfire-soc/hart-software-services/commit/b3c277c69cba09b66449b99e8716cd82add8a876
- Add the delay function mmc_delay(MASK_8BIT); in the line 787 of mss_mmc.c file:
- Add the delay function mmc_delay(MASK_8BIT); in the line 787 of mss_mmc.c file:
- Edit Makefile in hart-software-services-2023.02 Folder for example for TEM0007 as shown:Makefile of hart-software-services-master folder
- Copy def_config file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste it in hart-software-services-master folder and rename it to .config file.
- Edit .config file according to your module. For example for TEM0007 is edited this file as shown:
#
# Board/Design Configuration Options
#
#
# TEM0007 Trenz electronic GmbH polarfire SoC module Design Configuration Options
#
CONFIG_SOC_FPGA_DESIGN_XML="boards/TEM0007/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml"
# end of TEM0007 Design Configuration Options
# end of Board/Design Configuration Options
#
# Services
#
CONFIG_SERVICE_BEU=y
CONFIG_SERVICE_BOOT=y
#
# Boot Service
#
# CONFIG_SERVICE_BOOT_USE_PAYLOAD is not set
# CONFIG_SERVICE_BOOT_CUSTOM_FLOW is not set
CONFIG_SERVICE_BOOT_DDR_TARGET_ADDR=0x8e000000
CONFIG_SERVICE_BOOT_MMC_USE_GPT=y
# end of Boot Service
CONFIG_SERVICE_DDR=y
CONFIG_SERVICE_GOTO=y
CONFIG_SERVICE_IPI_POLL=y
CONFIG_SERVICE_MMC=y
#
# MMC
#
#
# MMC Mode
#
# CONFIG_SERVICE_MMC_MODE_EMMC is not set
CONFIG_SERVICE_MMC_MODE_SDCARD=y
# end of MMC Mode
#
# MMC Voltage
#
# CONFIG_SERVICE_MMC_BUS_VOLTAGE_1V8 is not set
# end of MMC Voltage
#
# SDIO Control
#
CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT=y
CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS=0x4fffff00
# end of SDIO Control
CONFIG_SERVICE_MMC_SPIN_TIMEOUT=y
# CONFIG_SERVICE_MMC_SPIN_TIMEOUT_ASSERT is not set
CONFIG_SERVICE_MMC_SPIN_TIMEOUT_MAX_SPINS=1000000
# end of MMC
CONFIG_SERVICE_OPENSBI=y
CONFIG_SERVICE_OPENSBI_IHC=y
CONFIG_SERVICE_OPENSBI_RPROC=y
# CONFIG_SERVICE_POWERMODE is not set
# CONFIG_SERVICE_QSPI is not set
CONFIG_SERVICE_SCRUB=y
#
# RAM Scrubbing Service
#
CONFIG_SERVICE_SCRUB_MAX_SIZE_PER_LOOP_ITER=4096
CONFIG_SERVICE_SCRUB_RUN_EVERY_X_SUPERLOOPS=256
# CONFIG_SERVICE_SCRUB_CACHED_DDR is not set
# end of RAM Scrubbing Service
CONFIG_SERVICE_SGDMA=y
# CONFIG_SERVICE_SPI is not set
CONFIG_SERVICE_TINYCLI=y
#
# Tiny Command Line Interface
#
CONFIG_SERVICE_TINYCLI_TIMEOUT=1
CONFIG_SERVICE_TINYCLI_REGISTER=y
# CONFIG_SERVICE_TINYCLI_MONITOR is not set
# CONFIG_SERVICE_TINYCLI_ENABLE_PREBOOT_TIMEOUT is not set
# end of Tiny Command Line Interface
# CONFIG_SERVICE_UART is not set
CONFIG_SERVICE_USBDMSC=y
#
# USB Device Mass Storage Class
#
CONFIG_SERVICE_USBDMSC_REGISTER=y
# CONFIG_SERVICE_USBDMSC_ENABLE_MAX_SESSION_TIMEOUT is not set
# end of USB Device Mass Storage Class
CONFIG_SERVICE_WDOG=y
#
# Watchdog Service
#
# CONFIG_SERVICE_WDOG_DEBUG is not set
CONFIG_SERVICE_WDOG_DEBUG_TIMEOUT_SEC=240
CONFIG_SERVICE_WDOG_ENABLE_E51=y
# end of Watchdog Service
# CONFIG_SERVICE_YMODEM is not set
# end of Services
#
# General Configuration Options
#
#
# Miscellaneous
#
#CONFIG_USE_PCIE=y
CONFIG_USE_PCIE=n
CONFIG_OPENSBI=y
CONFIG_USE_IHC=y
#
# Tamper
#
# CONFIG_USE_TAMPER is not set
# end of Tamper
CONFIG_ALLOW_COLDREBOOT=y
#
# Cold Reboot
#
CONFIG_ALLOW_COLDREBOOT_ALWAYS=y
# CONFIG_ALLOW_COLDREBOOT_ON_OPENSBI_FAULT is not set
# end of Cold Reboot
# end of Miscellaneous
#
# OpenSBI
#
# CONFIG_PROVIDE_DTB is not set
# end of OpenSBI
#
# Memory Options
#
# CONFIG_SKIP_DDR is not set
# CONFIG_MEMTEST is not set
# CONFIG_USE_PDMA is not set
# CONFIG_INITIALIZE_MEMORIES is not set
# end of Memory Options
# end of General Configuration Options
#
# Build Options
#
CONFIG_COLOR_OUTPUT=y
CONFIG_USE_LOGO=y
#
# Logo
#
CONFIG_LOGO_INVERT_COLORS=y
# end of Logo
# CONFIG_CC_STACKPROTECTOR_STRONG is not set
# CONFIG_CC_DUMP_STACKSIZE is not set
# CONFIG_LD_RELAX is not set
CONFIG_CC_USE_MAKEDEP=y
CONFIG_CC_USE_GNU_BUILD_ID=y
CONFIG_CC_HAS_INTTYPES=y
CONFIG_DISPLAY_TOOL_VERSIONS=y
# CONFIG_LOG_FUNCTION_NAMES is not set
# end of Build Options
#
# Compression
#
CONFIG_COMPRESSION=y
CONFIG_COMPRESSION_MINIZ=y
# end of Compression
#
# Crypto
#
# CONFIG_CRYPTO_SIGNING is not set
# end of Crypto
#
# Debug Options
#
CONFIG_DEBUG_LOG_STATE_TRANSITIONS=y
CONFIG_DEBUG_LOOP_TIMES=y
CONFIG_DEBUG_LOOP_TIMES_THRESHOLD=2500000
# CONFIG_DEBUG_IPI_STATS is not set
# CONFIG_DEBUG_CHUNK_DOWNLOADS is not set
# CONFIG_DEBUG_MSCGEN_IPI is not set
# CONFIG_DEBUG_PROFILING_SUPPORT is not set
CONFIG_DEBUG_PERF_CTRS=y
CONFIG_DEBUG_PERF_CTRS_NUM=16
# CONFIG_DEBUG_RESET_REASON is not set
# end of Debug Options
#
# SSMB Options
#
# CONFIG_HSS_USE_IHC is not set
CONFIG_IPI_MAX_NUM_QUEUE_MESSAGES=8
# CONFIG_IPI_FIXED_BASE is not set
# end of SSMB Options
- Edit .config file according to your module. For example for TEM0007 is edited this file as shown:
- Now HSS workspace is ready to be compiled. Right click on hart-software-services-2023.02 and click on Build Project.
- After compiling a config.h will be generated in the hart-software-services-2023.02 folder. By opening this header file it can be seen all configurations of .config file.
Software Design - Yocto
Trenz electronic has developed his own BSP for Microchip devices same as polarfire soc in Yocto. In the following will be explained the folders in detail.
meta-trenz-polarfire-bsp Folder | Description |
---|---|
recipes-apps | Contains of start up application for executing of init.sh by booting. |
recipes-bsp | Contains of uboot necessary files same as *.bbappend files, device tree and etc. |
recipes-core | Contains of *.bb file for Trenz defined image version. In this file are defined necessary packets or files that must be installed in linux. |
recipes-kernel | Contains of kernel necessary files same as *.bbappend files, device tree, config files and etc. |
recipes-tools | Contains of *.bbappend file |
tools | Contains of manifest xml file to define necessary meta data that are required. |
wic | Contains *.wks file that decrips disk image properteis |
In the following table exists more information about required packets and supported version.
Meta data | Supported Version | Description |
---|---|---|
meta-riscv | Kirkstone | |
openembedded-core | Kirkstone | |
meta-openembedded | Kirkstone | |
meta-polarfire-soc-yocto-bsp | 2022.11 |
Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed automatically. The user needs only to write the image file on the SD card. To prepare the image file :
- Download and save meta-trenz-polarefile-bsp folder in the host linux and execute its shell script as shown:
. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh
- After compiling image file *.img and its converted zip file *.zip will be saved in trenz bsp folder:
- <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
- <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip
U-Boot
File location: meta-trenz-<SoC name>-bsp/recipes-bsp/u-boot/
Changes:
CONFIG_PHY_MARVELL=y
CONFIG_DEFAULT_DEVICE_TREE="tem0007"
CONFIG_DEFAULT_FDT_FILE="tem0007.dtb"
CONFIG_OF_LIST="tem0007"
CONFIG_DM_GPIO=y
CONFIG_CMD_GPIO=y
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=y
CONFIG_LOG_CONSOLE=y
CONFIG_NVMEM=y → to be able to read MAC vom EEPROM
CONFIG_DM_RTC=y
Device Tree
U-boot Device Tree
// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ / { aliases { cpu1 = &cpu1; cpu2 = &cpu2; cpu3 = &cpu3; cpu4 = &cpu4; }; };
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2021 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ /dts-v1/; #include "microchip-mpfs.dtsi" #include "dt-bindings/gpio/gpio.h" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 / { model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { serial1 = &uart1; ethernet0 = &mac0; spi0 = &qspi; }; chosen { stdout-path = "serial1"; }; cpus { timebase-frequency = <RTCCLK_FREQ>; }; ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; clocks = <&clkcfg CLK_DDRC>; status = "okay"; }; usb_phy: usb_phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; reset-names = "OTG_RST"; }; }; &uart1 { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-mmc-highspeed; cap-sd-highspeed; cd-debounce-delay-ms; card-detect-delay = <200>; // mmc-ddr-1_8v; // mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &i2c1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; //compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; &refclk { clock-frequency = <125000000>; }; &mac1 { status = "disabled"; }; &mac0 { status = "okay"; phy-mode = "sgmii"; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &qspi { status = "okay"; num-cs = <1>; flash0: spi-nor@0 { compatible = "spi-nor"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <20000000>; spi-cpol; spi-cpha; }; }; &usb { status = "okay"; dr_mode = "otg"; // dr_mode = "host"; phys = <&usb_phy>; };
Kernel Device Tree
// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; #include "mpfs.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> /* Clock frequency (in Hz) of the rtcclk */ #define MTIMER_FREQ 1000000 / { #address-cells = <2>; #size-cells = <2>; model = "Trenz TEM0007"; compatible = "trenz,tem0007","microchip,mpfs"; aliases { ethernet0 = &mac0; serial0 = &mmuart0; serial1 = &mmuart1; serial2 = &mmuart2; serial3 = &mmuart3; serial4 = &mmuart4; }; chosen { stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = <MTIMER_FREQ>; }; //******************************************************// ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; fabricbuf0ddrc: buffer@A0000000 { compatible = "shared-dma-pool"; reg = <0x0 0xA0000000 0x0 0x2000000>; no-map; }; }; udmabuf0 { compatible = "ikwzm,u-dma-buf"; device-name = "udmabuf-ddr-c0"; minor-number = <0>; size = <0x0 0x2000000>; memory-region = <&fabricbuf0ddrc>; sync-mode = <3>; }; //******************************************************// usb_phy: usb_phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; reset-names = "OTG_RST"; }; soc { dma-ranges = <0 0 0 0 0x40 0>; }; }; &gpio1 { status = "okay"; }; &gpio2 { interrupts = <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>; status = "okay"; }; &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; //compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; &mac0 { status = "okay"; phy-mode = "sgmii"; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &mbox { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-mmc-highspeed; // mmc-ddr-1_8v; // mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &mmuart1 { status = "okay"; }; &mmuart2 { status = "okay"; }; &mmuart3 { status = "okay"; }; &mmuart4 { status = "okay"; }; &qspi { status = "okay"; num-cs = <1>; }; &refclk { clock-frequency = <125000000>; }; &spi0 { status = "okay"; }; &usb { status = "okay"; dr_mode = "otg"; // dr_mode = "host"; phys = <&usb_phy>; }; &syscontroller { status = "okay"; };
Kernel
File location: meta-trenz-<SoC name>-bsp/recipes-kernel/linux/
Changes:
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon=sbi root=/dev/mmcblk0p3 rootwait uio_pdrv_genirq.of_id=generic-uio"
CONFIG_EEPROM_AT24=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYS=y
CONFIG_REGMAP_I2C=y
- CONFIG_MARVELL_PHY=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_CLASS=y
CONFIG_NEW_LEDS=y
CONFIG_GPIOLIB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n
CONFIG_MTD_UBI=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_UBIFS_FS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y
CONFIG_MFD_SENSEHAT_CORE=m
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_AUXDISPLAY=y
CONFIG_SENSEHAT_DISPLAY=m
CONFIG_HTS221=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_MAGN_3AXIS=m
#CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
Images
Image recipe for minimal console image
File location: meta-trenz-<SoC name>-bsp/recipes-core/images/
Image recipes:
- te-image-minimal.bb: create minimal linux image
Added packages/recipes:
startup
iputils-ping
expect
rsync
rng-tools
iperf3
devmem2
can-utils
usbutils
pciutils
polarfire-soc-linux-examples
dt-overlay-mchp
libgpiod
libgpiod-tools
libgpiod-dev
i2c-tools
vim vim-vimrc
net-tools
htop
iw
python3
python3-pip
python3-flask
python3-flask-dev
python3-werkzeug
libudev
glib-2.0
sqlite3
dtc
cmake
tar
wget
zip
mtd-utils
mtd-utils-ubifs
Rootfs
Used filesystem: Root file system (RootFS)
Appx. A: Change History and Legal Notices
Document Change History
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Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
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REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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