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CompanyTrenz Electronic GmbH
PCN NumberPCN-20200615
TitleTE0835-01 to TE0835-02 Hardware Revision Change
SubjectHardware Revision Change
Issue Date


Products Affected

This change affects all Trenz Electronic TE0835 SoMs of revision 01: TE0835-01-*.

Affected Product



#1 Added VRP resistor on bank 65

Type: Schematic change

Reason:  Some I/O standards with DCI need external VRP.

Impact: DCI I/O standarts with external VRP usable on this bank.

#2 LDO U33 is changed on ADP7102ACPZ

Type: Schematic change

Reason: Primilary installed LDO had disadvantegous output discarge function, which prevents external sourcing of 3.3V_CPLD rail.

Impact: External sourcing of 3.3V_CPLD rail possible.

#3 Changed assignment of Signal DBG_LED3 at SoC

Type: Schematic change

Reason: Improve routing/signal integrity.

Impact: Signal DBG_LED3 is connected on AD18 pin of FPGA, was AE18.

#4 Changed assignment of Signal FPGA IO0 at SoC

Type: Schematic change

Reason: Improve routing/signal integrity.

Impact: Signal FPGA_IO0 to CPLD now available at Pin AE18, was AF17.

#5 Signal MIO13_25 connected to J1 pin 33 instead of MIO25

Type: Schematic change

Reason: PS periphery controller with fixed IO assignments may need MIO13 (e.g. for eMMC).

Impact: MIO13 now availabe at B2B J1, if still MIO25 is needed a jumper resistor has to moved from R76 to R84.

#6 Resistor R84 is removed

Type: Schematic change

Reason: MIO13 is now user IO.

Impact: No pullup on MIO13.

#7 LED D1 moved on edge of PCB and controlled via CPLD Signal PWR_STATUS

Type: PCB change

Reason: MIO13 is now user IO.

Impact: It is no more possible to control LED D1 via MIO13.

#8 Added THT testpoints on CPLD_JTAGEN, R76 was removed

Type: Schematic change

Reason: Improve solution for enabling CPLD JTAG.

Impact: CPLD update possible when JTAG enabled via shortcut of THT testpoints, also installation of pinheader with jumper possible.

#9 Signals B49_XX_X are renamed in B88_XX_X

Type: Schematic change

Reason: Inconsistent net naming.

Impact: Nets named according to resident Bank.

#10 C241 is changed to 1nF

Type: BOM change

Reason: Compensation of U7 did not work.

Impact: U7 stable working.

#11 Improved length matching of CLK signals on RFADC and RFDAC

Type: PCB change

Reason: Lenght matching required.

Impact: Clks correctly length matched.

#12 Connection of U8  fixed (PCB)

Type: PCB change

Reason: BIAS routed to wrong Powerrail.

Impact: U8 working correctly.

#13 PGOOD of U7 connected exclusively to pin E7

Type: Schematic change

Reason: PGOOD did not work.

Impact: PGOOD of U7 works correct.

Method of Identification

The revision number is printed on the top side of the PCB.

Production Shipment Schedule

The new revison 02 is available from August 2020.

Contact Information

If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at


Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances.  For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.

This PCN follows JEDEC Standard J-STD-046.

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