This document provides a brief overview of the required board configuration (DIP switches, jumpers, etc.) for each supported module when used with the TE0701 carrier board. It describes the settings required for each module, including the boot mode configuration where applicable.
| DIP/Jumper/Button | TE0701-06 | TE0720-02/-03/-04 | ... |
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| S3 | | DIP* | Description |
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| S3-1 (M2) | CM1: NOSEQ signal to the module | | S3-2 (M1) | CM0: JTAGMODE, access to the module CPLD (PCB REV07 or newer, not used on REV06) | | S3-3 (ENJTAG) | JTAGEN: JTAG target (module or carrier CPLD) | | S3-4 | MIO0 (Pmod J1-1, JB1-88), depends on the module |
* Close Dip (ON) will force to GND Board labels in brackets, signal names from the schematic. | S3-1 (NOSEQ): - ON = NOSEQ low, normal power sequencing of the TE0720.
- OFF = NOSEQ high, the 1.0V and 1.8V supplies of the module are always on (only intended for VIN = 3.3V, the TE0701 supplies 5V).
- Recommended: ON.
S3-2 (JTAGMODE): - no function on TE0701-06.
- Recommended: OFF.
S3-3 (JTAGEN): | JTAG MUX | Carrier CPLD | Module SoC |
|---|
| S3-3 | OFF | ON |
Module CPLD (TE0720): - not accessible via TE0701-06,
- JTAGMODE is not connected to the B2B connector.
S3-4 (MIO0): - not used by the TE0720 reference design (GPIO with pull-up).
- Recommended: OFF.
Labels on the board: - M2 = S3-1,
- M1 = S3-2,
- ENJTAG = S3-3.
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| S4 | | DIP* | Description |
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| S4-1 | VID0: FMC_VADJ voltage | | S4-2 | VID1: FMC_VADJ voltage | | S4-3 | VID2: FMC_VADJ voltage | | S4-4 | CM2: PGOOD signal to the module (boot mode) |
| S4-3 | S4-2 | S4-1 | FMC_VADJ |
|---|
| ON | ON | ON | 3.3V | | ON | ON | OFF | 2.5V | | ON | OFF | ON | 1.8V | | ON | OFF | OFF | 1.5V | | OFF | ON | ON | 1.25V | | OFF | ON | OFF | 1.2V | | OFF | OFF | ON | 0.8V, do not use (not supported as VCCIO standard) | | OFF | OFF | OFF | controlled via I2C (default 1.8V), see TE0701 CPLD |
* Close Dip (ON) will force to GND | S4-4 (Boot Mode): | Boot Mode* | QSPI | SD | JTAG |
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| S4-4 | OFF | OFF | ON | | SD card (J8) | not inserted | inserted | inserted |
Module CPLD firmware dependent: - TE0720 CPLD REV07 uses PGOOD (S4-4) and MODE (SD card detect J8) as boot mode pins.
- S4-4 ON without SD card: not defined.
Older TE0720 CPLD firmware (REV06 or older): - PGOOD is not a boot mode pin,
- SD card inserted = SD boot, otherwise QSPI.
FMC_VADJ settings for the TE0720: see J16/J17/J21. |
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| S1 | User push button, function depends on the CPLD firmware (AMD modules: shows register GPIO_output[23:16] on LEDs D1 ... D8) | -- |
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| S2 | Reset, push button will force to GND (global reset of the attached module) | Module reset via RESIN (JM2-18), handled by the TE0720 CPLD |
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| J16/J17/J21 | VCCIO Power supply | Baseboard voltage | B2B pins | 4 x 5 SoM VCCIO pins |
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| VIOTA | JB2-2/4/6 | VCCIOB (JM2-1/3), VCCIOC (JM2-5) | | VIOTB | JB1-10/12, JB2-8/10 | VCCIOA (JM1-9/11), VCCIOD (JM2-7/9) |
| Voltage | VIOTA | VIOTB |
|---|
| 3.3V | J17: 1-2, J16: open | J17: 1-2, J16: open, J21: 1-2 | | 2.5V | J17: 2-3, J16: open | J17: 2-3, J16: open, J21: 1-2 | | FMC_VADJ (S4) | J17: open, J16: 1-2 | J21: 2-3 |
J21: - 1-2 = VIOTB same as VIOTA,
- 2-3 = VIOTB from FMC_VADJ.
Set and measure the voltages before mounting the module. | Reference design (te0720-rd): - bank 34 with LVCMOS33,
- VIOTA = 3.3V
- VIOTB = VIOTA
| Baseboard voltage | TE0720 bank | Allowed range |
|---|
| VIOTA | VCCIO34 (JM2-1/3), VCCIO33 (JM2-5) | 1.425V ... 3.465V (VCCIO34), must always be powered | | VIOTB | VCCIO35 (JM1-9/11), VCCIO13 (JM2-7/9) | 1.14V ... 3.465V |
| Voltage | VIOTA | VIOTB |
|---|
| 3.3V | yes | yes | | 2.5V | yes | yes | | FMC_VADJ 1.8V / 1.5V | yes | yes | | FMC_VADJ 1.25V / 1.2V | do not use, out of range! | yes | | FMC_VADJ 0.8V | do not use | do not use |
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| J9/J19/J20 | USB VBUS (Micro-USB J12) | USB mode | J9 | J19 |
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| Host (5V0 intern) | 1-2 | 1-2 | | Device (VBUS extern) | 2-3 | open |
J20: 1-2 = additional decoupling capacitor 200 µF | | USB mode | Host | Device |
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| J9 | 1-2 | 2-3 | | J19 | 1-2 | open |
Reference design (te0720-rd): |
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| J18 | 12V on CameraLink pin 26 (J18: 1-2), default open | -- |
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| J7 | USB to JTAG/UART Interface (on-board FTDI FT2232H, Mini-USB) - Channel A: JTAG, target selected with S3-3
- Channel B: UART to the module (MIO14/MIO15)
Do not access the FTDI EEPROM with FTDI tools, this erases the AMD JTAG license. | PS UART on MIO14/MIO15 (JM1-92/JM1-85) |
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| CPLD Dependencies | yes - CPLD on carrier TE0701: TE0701 CPLD
- Firmware REV06 for PCB REV06: use the default variant for AMD modules (SC-PGM-TE0701-06_CC701-6P0_default_...)
- S3/S4 functions on this page: firmware REV06
| yes - CPLD on module TE0720: TE0720 CPLD
- Firmware REV07 (PCB REV02 ... REV04): PGOOD used as boot mode pin
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| HW Revision Dependencies | PCN-20161128 TE0701-05 to TE0701-06 Hardware Revision Change yes, for older revisions (REV05 or older): - no DIP switch S4 and no jumper J16 (FMC_VADJ not adjustable)
- CPLD firmware REV06 not supported
| TE0720 TRM (Hardware Revision History) yes - boot mode pins depend on the CPLD firmware, see CPLD dependencies
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