Table of contents


CPLD Access  

Set B2B Pin JM1-89 (JTAGEN) to VDD (3.3V)


With TE0701:

  • not possible on TE0701-01 up to TE0701-06

With TE0703:

  • Set S2-2 dip switch of TE0703 to  OFF
  • Set S2-3 dip switch of TE0703 to OFF
  • Program the special TE0703 CPLD Firmware *.jed file on the CPLD of TE0703. This jed file exists in optional folder.
  • Set S2-3 dip switch of TE0703 to ON
  • Now the CPLD of TE0715 can be accessed.

With TE0705:

  • For TE0705 PCB REV03 :

    • Set S3-3 (ENJTAG) to OFF
    • Program the special TE0705 CPLD firmware (*.jed file) on the CPLD of TE0705. This jed file exists in optional folder.
    • Set S3-1 (CM1) of TE0705 to ON
    • Set S3-2 (CM0) of TE0705 to ON
    • Set S3-3 (EJTAG) of TE0705 to ON
    • Now the CPLD of TE0715 can be accessed.
  • For TE0705 PCB REV04 or later:
    • Set S3-3 (ENJTAG) to OFF 
    • Program the default jed file on the CPLD of TE0705 , If the default firmware does not exist on the CPLD of TE0705.
    • Set the S4-1 (USR0) dip switch to ON
    • Set the S4-4 (USR3) dip switch to ON
    • Set the S3-3 (EJTAG) dip switch to ON
    • Now the CPLD of TE0715 can be accessed.

With TE0706:

  • not possible

Available CPLD Firmware

Download

  • TE0715/<PCB Revision>/Firmware/
    • Use files from the subfolders of your PCB revision

General instructions

CPLD Firmware Update - General Requirements

  • Lattice Diamond or Lattice Diamond Programmer is available for free on http://www.latticesemi.com/
  • Lattice compatible JTAG Programmer, for example:
    • Trenz TE0790 or Carrier with FTDI for JTAG
    • Most JTAG programmer, which used FTDI Chip to translate USB to JTAG
      • Digilent FTDI based programmer are not compatible with Lattice.
  • JTAG must be connected to CPLD JTAG
  • JTAG Enable Pin of CPLD must be selectable and set to VDD
  • Correct CPLD Firmware (JED-File) from Trenz Electronic Download

CPLD Firmware Update - General Procedure

Important:

  • Connect only one JTAG device to host PC.
  • Close all other JTAG programs, like Xilinx tools (on WinOS check hw_server.exe is terminated).

Procedure:

  1. Enable CPLD JTAG access (See JTAG section on CPLD Firmware description)
  2. Connect JTAG
  3. Power on System
  4. Open Lattice Diamond Programmer
  5. Detect Cable and click "Ok"
    For some devices second Port must be selected:
  6. Select Device (See CPLD Firmware overview description).
    In the most cases select the correct detected device one time (it's yellow at first on the menue)
  7. Select correct Firmware from Download Area (JED File)
  8. Program CPLD:
  9. Disable CPLD JTAG access (See JTAG section on CPLD Firmware description)
  10. Restart System

More Information are available on the CPLD Firmware description and on the readme.txt included into the download zip.


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