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Firmware for PCB CPLD with designator U26 : LCMX02-256HC

Feature Summary

  • Power Management
  • Reset
  • Boot Mode
  • PUDC
  • ETH
  • LED
  • I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
CONFIGout4NONE1.8VETH config pin
EN1 / EN1in32UP3.3VINB2B Power Enable - Old name from PCB REV04 and earlier : EN1 / EN_SC3
JTAGEN / ---in26---3.3VINJTAG enable for CPLD Firmware update
MODE /MODEin30UP3.3VINB2B Boot Mode Pin- Old name from PCB REV04 and earlier :  MODE /MODE_SC1
MODE0_R / MODE0_Rout12NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE0_R / BOOT_R0
MODE2_R / MODE2_Rout17NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE2_R / BOOT_R2
MODE3_R / MODE3_Rout13NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE3_R / BOOT_R3
MR / MRout10UP3.3VZynq Reset - Old name from PCB REV04 and earlier : MR / POR_B
SPI_SCK_FB/VCFG1out8NONE3.3VOnly for PCB REV05 and later. This pin is connected to MIO8 to change Bank 1 voltage for some applications like boundary scan to test MIOs.
RST / ------9---3.3V/ currently_not_used
NOSEQ / NOSEQinout29UP3.3VINNOSEQ pin- Old name from PCB REV04 and earlier : NOSEQ / NOSEQ_SC4
PG_3V3 / PG_3V3in28UP3.3VINPower Good- Old name from PCB REV04 and earlier :  PG_3V3 / PG_1V5

Power Good -  Old name from PCB REV04 and earlier:  PG_DDR_PWR / PG_1V8

PG_MGT / PG_MGTin11NONE3.3V/ currently_not_used
PGOOD / PGOODinout1UP3.3VINB2B Power Good- Old name from PCB REV04 and earlier :  PGOOD / STAT_SC2
RESIN / RESINin23UP3.3VINB2B Reset - Old name from PCB REV04 and earlier :  RESIN / nRST_SC0
SCL33 / SCL33in14UP3.3VI2C clock pin- Old name from PCB REV04 and earlier :  SCL33 / SCL
SDA33 / SDA33inout16UP3.3VI2C data pin- Old name from PCB REV04 and earlier :  SDA33 / SDA
X0 / X0out21NONEVCCIO34FPGA Pin K8 - Old name from PCB REV04 and earlier : X0 / XA_SC
X1 / X1out20NONEVCCIO34PUDC FPGA Pin K7- Old name from PCB REV04 and earlier : X1 / XB_SC

Functional Description


JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN pin of CPLD (pin 26) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.

CPLD JTAGEN (B2B JM1-89)Description
0FPGA access
1CPLD access


PGOOD  is  PG_3V3 and PG_ALL and EN1. There is no additional power control.


POR_B is RESIN and PG_3V3 and PG_ALL and EN1 with some delay.


X1 can be changed by changing  PUDC generic parameter in firmware source code. In released zip folder can be found all jed file according to PUDC state options.

Boot Mode

Boot mode can be set either by hardware (dip-switch) on the carrier board or by Linux console. Even after booting you can change the boot mode. After changing the boot mode FPGA is restarted automatically by CPLD. To change boot mode a state machine  continuously monitors the corresponding register that can be change via I2C interface between CPLD and FPGA. After changing this register according to desired boot mode , CPLD will reset FPGA.

Change MethodBoot ModeCPLD PGOOD Pin (B2B Pin JM1-30)CPLD MODE Pin (B2B Pin JM1-32)Description
HardwareSD Card10
Change MethodBoot ModeCommand in Linux consoleCommand in FSBLDescription
i2cset -y 0 0x20 0x1 0x91
0x20 is device address. 0x1 is register address.
SoftwareSD Card
i2cset -y 0 0x20 0x1 0x93

i2cset -y 0 0x20 0x1 0x92


CONFIG is constant zero. PHY_LED1 is connected to X0.

FSBL code

CPLD revision,Boot mode and other features of the board will be shown by FSBL code  while booting.The format of these information are shown in the following:

CPLD RevisionSoftware adjusted boot modeExisted boot modes in the programmed jed FilePUDC ModeCurrent boot modeDescription

Deactive (0)0 (QSPI/SD)Pull-up activated (0)JTAG (0)
Active (1)1 (QSPI/JTAG)Pull-up deactivated (1)QSPI (2)
----2 (JTAG/SD)----SD Card (3)
----3 (default QSPI/JTAG/SD)--------

Boundary scan

To implement boundary scanning (especially after the production of the board is necessary to test all MIOs), MIO bank voltage must be set to a certain value.

For more information refer to the following site :

From PCB revision 05 and later MIO8 state can be changed by CPLD. According the following table the MIO bank voltage can be determined for FPGA:

Bank VoltageBank 1 (related pin MIO8)Bank 0 (related pin MIO7)Description
2.5V / 3.3 V00MIO8 is pulled up in module hardware.
MIO7 is pulled down in module hardware.
1.8 V11Default value because of pull up resistor on the board

The bank 0 voltage is determined  in 2.5V / 3.3 V for FPGA by connecting MIO7 to GND. Bank 1 voltage can be determined for FPGA by changing the state of MIO8 in  linux console or in FSBL code:

Bank 1 Voltage Command in linux consoleCommand in FSBL codeDescription
2.5 V / 3.3 V
i2cset -y 0 0x20 0x1 0x61

Only for boundary scaning
MIO8 is set to low.
In this case FPGA will be reset and boot mode will be set in JTAG mode automatically.

1.8 V
i2cset -y 0 0x20 0x1 0x64

MIO8 is set to high impedance. Because of pull up resistor on the board MIO8 will be set on high.

As default MIO8 is set to high in the hardware to inform FPGA that  bank 1 voltage is 1.8V. To implement boundary scan it is necessary to change MIO8 state to low. After changing the MIO8 state to low, FPGA will be reset and set in JTAG boot mode by CPLD automatically.


LED stateDescription
Blink sequence   ********Reset is active. (RESIN = '0')
Blink sequence   *****oooBoth boot mode and MIO8 state in linux console or in FSBL code are not changed.
Blink sequence   ****ooooBoot mode is changed by software either in linux console or by FSBL code.
Blink sequence   ***oooooMIO8 stateis changed in linux console or in FSBL code.

Appx. A: Change History and Legal Notices

Revision Changes

  • Changes REV02 to REV03
    • Boot mode configuration via hardware (dip switch) and firmware added (Boot mode configuration via linux console)
    • Pullup or pulldown states of PORT pins was checked.
    • Adding i2c to gpio ip (i2c_slave.vhd) 
    • Changing oscillator frequency from 12.09 MHZ to 24.18MHZ
    • PORT signals according to the schematic are renamed.
    • JTAG time constraint correction.
    • PGOOD pin is used as boot mode selector pin.
    • VCFG1 (MIO8) pin can be changed by i2cset command. This pin must be grounded by boundary scanning.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

  • working in process


v.6REV02REV04,REV03John Hartfiel
  • REV02 , Firmware released  2015-08-18


Initial release


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