Table of contents
Firmware for PCB CPLD with designator U26 : LCMX02-256HC
- Power Management
- CPLD JTAG
- Boot Mode
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Bank Power||Description|
|/ LED||out||25||3.3VIN||Red LED D3|
|CONFIG||out||4||1.8V||ETH config pin|
|EN1 / EN_SC3||in||32||3.3VIN||B2B Power Enable|
|JTAGEN||in||26||3.3VIN||JTAG enable for CPLD Firmware update|
|MODE /MODE_SC1||in||30||3.3VIN||B2B Boot Mode Pin|
|MODE0_R / BOOT_R0||out||12||3.3V||Zynq Boot Mode Pin|
|MODE2_R / BOOT_R2||out||17||3.3V||Zynq Boot Mode Pin|
|MODE3_R / BOOT_R3||out||13||3.3V||Zynq Boot Mode Pin|
|MR / POR_B||out||10||3.3V||Zynq Reset|
|NOSEQ / NOSEQ_SC4||in||29||3.3VIN||/ currently_not_used|
|PG_3V3 / PG_1V5||in||28||3.3VIN||Power Good|
|PG_DDR_PWR / PG_1V8||in||27||3.3VIN||Power Good|
|PGOOD / STAT_SC2||out||1||3.3VIN||B2B Power Good|
|PHY_LED1||in||5||1.8V||PHY LED Pin|
|RESIN / nRST_SC0||in||23||3.3VIN||B2B Reset|
|SCL33 / SCL||in||14||3.3V||/ currently_not_used|
|SDA33 / SDA||inout||16||3.3V||/ currently_not_used|
|X0 / XA_SC||out||21||VCCIO34||FPGA Pin K8|
|X1 / XB_SC||out||20||VCCIO34||PUDC FPGA Pin K7|
PGOOD is PG_3V3 and PG_DDR_PWR and EN1
There is no additional power control.
POR_B is RESIN and PG_3V3 and PG_DDR_PWR and EN1 with some delay.
X1 is constant high. Pullups disabled.
- MODE0_R is constant one.
- MODE2_R is not MODE.
- MODE3_R is constant zero.
CONFIG is constant zero.
PHY_LED1 is connected to X0.
LED is not POR_B.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
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