TE0715 CPLD

Overview

Firmware for PCB CPLD with designator U26 : LCMX02-256HC

Feature Summary

• Power Management
• Reset
• CPLD JTAG
• Boot Mode
• PUDC
• ETH
• LED
• I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN pin of CPLD (pin 26) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.

Power

PGOOD  is  low if  one of the PG_3V3 ,PG_ALL ,EN1 or PG_MGT signals is low otherwise it's high impedance. PGOOD is a bidirectional signal. It is used as second boot mode selector pin too. There is no additional power control.

Reset

POR_B (MR signal) can be extracted by anding RESIN, PG_3V3, PG_MGT, PG_ALL and EN1 with some delay. RESIN is connected to a push button on the carrier board through B2B connector and probably a CPLD chip. It depends on which carrier bard is using.

PUDC

X1 can be changed by changing  PUDC generic parameter in firmware source code. In released zip folder can be found all jed file according to PUDC state options.

Boot Mode

Boot mode can be set either by hardware (dip-switch) on the carrier board or by software in Linux console or FSBL code. Even after booting boot mode can be changed. After changing the boot mode FPGA is restarted automatically by CPLD. To change boot mode a state machine  continuously monitors the corresponding register that can be change via I2C interface between CPLD and FPGA. After changing this register according to desired boot mode , CPLD will reset FPGA.

i2cset -y 0 0x20 0x01 0x91

iic_write8(0x20,0x01,0x91)

i2cset -y 0 0x20 0x01 0x93

iic_write8(0x20,0x01,0x93)

i2cset -y 0 0x20 0x01 0x92

iic_write8(0x20,0x01,0x92)

ETH

CONFIG is constant zero. PHY_LED1 is connected to X0.

I2C to GPIO

CPLD firmware consists of a I2C to GPIO block. This subsystem provides I2C protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via I2C bus interface protocol. The address of this block in the firmware is 0x20. In this case related I2C bus is bus 0 but the bus may be different. These registers can be accessed with I2C commands in linux console or with i2c functions in FSBL code. To access these registers the following commands in linux console can be used:

• To see the I2C bus addresses :                                     i2cdetect -y -r 0    

• To read register of I2C to GPIO module:                            i2cget -y 0 0x20 <register address>     

• To write data in a register of I2C to GPIO module:                 i2cset -y 0 0x20 <register address> <data>

I2C to GPIO is used to set boot mode in linux console or in FSBL code. It is used to activate boundary scan mode too.

NOSEQ

NOSEQ pin can be used by user as GPIO. In this case the following table is valid:

i2cset -y 0 0x20 0x02 0x00

i2cset -y 0 0x20 0x02 0x01

i2cget -y 0 0x20 0x02

Access to CPLD registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

i2cget -y 0 0x20 0x00

i2cget -y 0 0x20 0x01

i2cget -y 0 0x20 0x02

i2cget -y 0 0x20 0x03

i2cset -y 0 0x20 0x00 <data>

i2cset -y 0 0x20 0x01 <data>

i2cset -y 0 0x20 0x02 <data>

i2cset -y 0 0x20 0x03 <data>

To read NOSEQ pin : i2cget -y 0 0x20 0x02 --> Bit 0 shows NOSEQ pin state.

This bit is controlled by user to turn LED on or off.  To read this bit --> i2cget -y 0 0x20 0x03

Default is set to '1' after power on. For example to set NOSEQ pin low: i2cset -y 0 0x20 0x02 0x00

FSBL code

CPLD revision,boot mode and other features of the board will be shown by FSBL code in the linux console  while booting.The format of these information are shown in the following:

Boundary scan

To implement boundary scanning (especially after the production of the board is necessary to test all MIOs), MIO bank voltage must be set to a certain value.

For more information refer to the following site :https://support.xilinx.com/s/article/57930?language=en_US

From PCB revision 05 and later MIO8 state can be changed by CPLD. According the following table the MIO bank voltage can be determined for FPGA:

The bank 0 voltage is determined  in 2.5V / 3.3 V for FPGA by connecting MIO7 to GND. Bank 1 voltage can be determined for FPGA by changing the state of MIO8 in  linux console or in FSBL code:

i2cset -y 0 0x20 0x01 0x61

iic_write8(0x20,0x01,0x61)

----

----

As default MIO8 is set to high in the hardware to inform FPGA that  bank 1 voltage is 1.8V. To implement boundary scan it is necessary to change MIO8 state to low. After changing the MIO8 state to low, FPGA will be reset and set in JTAG boot mode by CPLD automatically.

LED (RED LED D3)

( * → LED ON; o → LED OFF)

i2cset -y 0 0x20 0x01 0x91
i2cset -y 0 0x20 0x01 0x92
i2cset -y 0 0x20 0x01 0x93 commands in linux console

i2cset -y 0 0x20 0x01 0x61 command in linux console

i2cset -y 0 0x20 0x03 0x00    → LED OFF
i2cset -y 0 0x20 0x03 0x01    → LED ON
0x20 is device address.0x03 is register address.

Appx. A: Change History and Legal Notices

Revision Changes

• Changes REV03 to REV04

  • PGOOD is always 'Z', if anding of power good signals (pg) is high. In last version it is valid only , if BOOTMODE_GEN is not equal to 3.

  • LED status is changed from *****ooo state to ON state for default status.

  • LED can be controlled by user. For this purpose user should give the following commands:

    • LED ON (Default) --> i2cset -y 0 0x20 0x03 0x01

    • LED OFF --> i2cset -y 0 0x20 0x03 0x00

  • PG_MGT used as power good same as PG_3V3. (IN) This pin is unused in older versions.

• Changes REV02 to REV03
  • Boot mode configuration via hardware (dip switch) and firmware added (Boot mode configuration via linux console)
  • Pullup or pulldown states of PORT pins was checked.
  • Adding i2c to gpio ip (i2c_slave.vhd) 
  • Changing oscillator frequency from 12.09 MHZ to 24.18MHZ
  • PORT signals according to the schematic are renamed.
  • JTAG time constraint correction.
  • PGOOD pin is used as boot mode selector pin.
  • VCFG1 (MIO8) pin can be changed by i2cset command. This pin must be grounded by boundary scanning.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices