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Overview

Zynq PS Design with Debian Desktop.

Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2019.2
  • Win32DiskImager
  • SD Card Formatter
  • Linux Debian 9 (Stretch) or Linux Ubuntu 18.04 (Bionic Beaver)
  • HDMI
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • Special FSBL for QSPI programming

Revision History

DateVivadoProject BuiltAuthorsDescription
2020-03-252019.2TE0726-zynqberrydemo2_noprebuilt-vivado_2019.2-build_8_20200325081643.zip
TE0726-zynqberrydemo2-vivado_2019.2-build_8_20200325081634.zip
Mohsen Chamanbaz/John Hartfiel
  • script update
2020-02-252019.2TE0726-zynqberrydemo2_noprebuilt-vivado_2019.2-build_6_20200225121842.zip
TE0726-zynqberrydemo2-vivado_2019.2-build_6_20200225121832.zip
Mohsen Chamanbaz
  • optional Ubuntu as root file system
2020-02-212019.2

TE0726-zynqberrydemo2_noprebuilt-vivado_2019.2-build_5_20200214101600.zip
TE0726-zynqberrydemo2-vivado_2019.2-build_5_20200214101548.zip

Mohsen Chamanbaz
  • update with Vivado 2019.2
2019-12-192018.3te0726-zynqberrydemo2_noprebuilt-vivado_2018.3-build_10_20200113155225.zip
te0726-zynqberrydemo2-vivado_2018.3-build_10_20200113155211.zip
Mohsen Chamanbaz
  • update with Vivado 2018.3
2018-11-19

2018.2

te0726-zynqberrydemo1_noprebuilt-vivado_2018.2-build_03_20181119110154.zip

te0726-zynqberrydemo1-vivado_2018.2-build_03_20181119110059.zip

Oleksandr Kiyenko
  • initial release (not published)
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
Flash Programming failed with 19.2Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 )2019.2 version
  • Option1:
    • In case Flash is empty, use fsbl_flash on programming GUI 
    • In case Flash is programmed use normal fsbl on programming GUI
  • Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
---
Known Issues

Requirements

Software

SoftwareVersionNote
Vitis2019.2needed, Vivado is included into Vitis installation
PetaLinux2019.2needed
Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
te0726-01 01 REV0164MB LPDDR216MB
not included, user modifications are needed
te0726-03r r REV02, REV03128MB DDR3L16MB
not included, user modifications are needed
te0726-03m m REV02, REV03512MB DDR3L16MB

te0726-03-07s-1c7sREV03512MB DDR3L16MB

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
---



Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB PowerUse USB2.0 or higher for power supply via USB
USB CableConnect to USB2 or better USB3 Hub for proper power supply over USB
MonitorDELL Model Number: U2412Mc
HDMI Cable--
Additional Hardware

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

TypeLocationNotes
------
Additional design sources

Prebuilt

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
      2. For 128MB and 64MB only:Netboot Offset must be reduced manually, see TE0726 Zynqberry Demo2#Config
    3. Build the Debian image/Ubuntu image file with executing the "mkdebian_Demo2_stretch.sh"/"mkubuntu_Demo2.sh" file in Linux Terminal
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<DDR size>", if exist, otherwise "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project folder>/_binaries_<Articel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

  1. Connect JTAG and power module (TE0726 can be powered via JTAG USB or external)
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash -swapp hello_te0726" possible
  4. Format the SD Card with SD Card Formatter or other tool
  5. Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
  6. Copy the Petalinux image.ub on SD-Card if you use Debian
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  7. Insert SD-Card

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described in section TE0726 Zynqberry Demo2#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Insert SD Card with image.ub
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
      Note: Wait until Linux boot finished For Linux Login use:
      1. User Name: root
      2. Password: root
  3. GUI starts for both variants Debian or Ubuntu automatically.
  4. Debian Desktop
    1. Web Browser Dillo open console and type dillo or use browser
    2. open console and start video or audio with "mplayer <video or audio file>"
  5. Ubuntu Desktop
    1. Web Browser Mozilla firefox can be used.
    2. Audio or Vider file can also be performed directly in GUI.

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

TypeNote
DDR---
QSPIMIO
USB0MIO, ETH over USB
SD1MIO
UART1MIO
I2C0EMIO
I2C1MIO
GPIOMIO / EMIO
USB RSTMIO
TTC0..1MIO
WDTMIO
AXI HP0..1
DMA0..1
PS Interfaces

Constraints

Basic module constraints

_i_bitgen_common.xdc
#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constraint

_i_common.xdc
#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
_i_te0726.xdc
#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o]
#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o]
 
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_1_tri_io[*]}]
# GPIO Pins
# GPIO2
set_property PACKAGE_PIN K15 [get_ports {GPIO_1_tri_io[0]}]
# GPIO3
set_property PACKAGE_PIN J14 [get_ports {GPIO_1_tri_io[1]}]
# GPIO4
set_property PACKAGE_PIN H12 [get_ports {GPIO_1_tri_io[2]}]
# GPIO5
set_property PACKAGE_PIN N14 [get_ports {GPIO_1_tri_io[3]}]
# GPIO6
set_property PACKAGE_PIN R15 [get_ports {GPIO_1_tri_io[4]}]
# GPIO7
set_property PACKAGE_PIN L14 [get_ports {GPIO_1_tri_io[5]}]
# GPIO8
set_property PACKAGE_PIN L15 [get_ports {GPIO_1_tri_io[6]}]
# GPIO9
set_property PACKAGE_PIN J13 [get_ports {GPIO_1_tri_io[7]}]
# GPIO10
set_property PACKAGE_PIN H14 [get_ports {GPIO_1_tri_io[8]}]
# GPIO11
set_property PACKAGE_PIN J15 [get_ports {GPIO_1_tri_io[9]}]
# GPIO12
set_property PACKAGE_PIN M15 [get_ports {GPIO_1_tri_io[10]}]
# GPIO13
set_property PACKAGE_PIN R13 [get_ports {GPIO_1_tri_io[11]}]
# GPIO16
set_property PACKAGE_PIN L13 [get_ports {GPIO_1_tri_io[12]}]
# GPIO17
set_property PACKAGE_PIN G11 [get_ports {GPIO_1_tri_io[13]}]
# GPIO18
set_property PACKAGE_PIN H11 [get_ports {GPIO_1_tri_io[14]}]
# GPIO19
set_property PACKAGE_PIN R12 [get_ports {GPIO_1_tri_io[15]}]
# GPIO20
set_property PACKAGE_PIN M14 [get_ports {GPIO_1_tri_io[16]}]
# GPIO21
set_property PACKAGE_PIN P15 [get_ports {GPIO_1_tri_io[17]}]
# GPIO22
set_property PACKAGE_PIN H13 [get_ports {GPIO_1_tri_io[18]}]
# GPIO23
set_property PACKAGE_PIN J11 [get_ports {GPIO_1_tri_io[19]}]
# GPIO24
set_property PACKAGE_PIN K11 [get_ports {GPIO_1_tri_io[20]}]
# GPIO25
set_property PACKAGE_PIN K13 [get_ports {GPIO_1_tri_io[21]}]
# GPIO26
set_property PACKAGE_PIN L12 [get_ports {GPIO_1_tri_io[22]}]
# GPIO27
set_property PACKAGE_PIN G12 [get_ports {GPIO_1_tri_io[23]}]
 
## DSI_D0_N
#set_property PACKAGE_PIN F13 [get_ports {GPIO_1_tri_io[24]}]
## DSI_D0_P
#set_property PACKAGE_PIN F14 [get_ports {GPIO_1_tri_io[25]}]
## DSI_D1_N
#set_property PACKAGE_PIN F12 [get_ports {GPIO_1_tri_io[26]}]
## DSI_D1_P
#set_property PACKAGE_PIN E13 [get_ports {GPIO_1_tri_io[27]}]
## DSI_C_N
#set_property PACKAGE_PIN E11 [get_ports {GPIO_1_tri_io[28]}]
## DSI_C_P
#set_property PACKAGE_PIN E12 [get_ports {GPIO_1_tri_io[29]}]
 
## CSI_D0_N
#set_property PACKAGE_PIN M11 [get_ports {GPIO_1_tri_io[30]}]
## CSI_D0_P
#set_property PACKAGE_PIN M10 [get_ports {GPIO_1_tri_io[31]}]
## CSI_D1_N
#set_property PACKAGE_PIN P14 [get_ports {GPIO_1_tri_io[32]}]
## CSI_D2_P
#set_property PACKAGE_PIN P13 [get_ports {GPIO_1_tri_io[33]}]
## CSI_C_N
#set_property PACKAGE_PIN N12 [get_ports {GPIO_1_tri_io[34]}]
## CSI_C_P
#set_property PACKAGE_PIN N11 [get_ports {GPIO_1_tri_io[35]}]
## PWM_R
##set_property PACKAGE_PIN N8 [get_ports {GPIO_1_tri_io[36]}]
## PWM_L
##set_property PACKAGE_PIN N7 [get_ports {GPIO_1_tri_io[37]}]
 
# PWM_R
set_property PACKAGE_PIN N8 [get_ports PWM_R]
# PWM_L
set_property PACKAGE_PIN N7 [get_ports PWM_L]
set_property IOSTANDARD LVCMOS33 [get_ports PWM_*]
_i_hdmi.xdc
set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p]
set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p]
 
set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}]
set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}]
set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}]
set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}]
_i_csi.xdc
set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p]
set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}]
set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}]
set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}]
set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}]
set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}]
# RPI Camera 1
create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p]
# RPI Camera 2.1
#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p]
_i_timing.xdc
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}]
set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_3]
set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_0]
 
set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D]
set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D]
 
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]
set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D]

Software Design - Vitis

For SDK project creation, follow instructions from:

Vitis

Application

SDK template in ./sw_lib/sw_apps/ available.

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • enable VTC and VDMA cores for debian desktop

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0726

Hello TE0726 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card

Changes:

  • # CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set

  • # CONFIG_SUBSYSTEM_ROOTFS_NFS is not set

  • CONFIG_SUBSYSTEM_ROOTFS_SD=y

  • # CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set

For 64MB variant only:

  • CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x2000000

For 128MB variant only:

  • CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x4000000

U-Boot

Start with petalinux-config -c u-boot
Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Device Tree

/include/ "system-conf.dtsi"
/ {
};
 
 
/ {
    #address-cells = <1>;
    #size-cells = <1>;
 
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        hdmi_fb_reserved_region@1FC00000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1FC00000 0x400000>;
            // 128M (R modules)
            //reg = <0x7C00000 0x400000>;
        };
        camera_fb_reserved_region@1F800000 {
            compatible = "removed-dma-pool";
            no-map;
            // 512M (M modules)
            reg = <0x1F800000 0x400000>;
            // 128M (R modules)
            //reg = <0x7800000 0x400000>;
        };
 
    };
 
    hdmi_fb: framebuffer@0x1FC00000 {           // HDMI out
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1FC00000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7C00000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
        status = "okay";
    };
 
    camera_fb: framebuffer@0x1F800000 {         // CAMERA in
        compatible = "simple-framebuffer";
        // 512M (M modules)
        reg = <0x1F800000 (1280 * 720 * 4)>;    // 720p
        // 128M (R modules)
        //reg = <0x7800000 (1280 * 720 * 4)>;   // 720p
        width = <1280>;                         // 720p
        height = <720>;                         // 720p
        stride = <(1280 * 4)>;                  // 720p
        format = "a8b8g8r8";
    };
 
    vcc_3V3: fixedregulator@0 {
        compatible = "regulator-fixed";
        regulator-name = "vccaux-supply";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
        regulator-always-on;
    };
};
 
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <50000000>;
        partition@0x00000000 {
            label = "boot";
            reg = <0x00000000 0x00500000>;
        };
        partition@0x00500000 {
            label = "bootenv";
            reg = <0x00500000 0x00020000>;
        };
        partition@0x00520000 {
            label = "kernel";
            reg = <0x00520000 0x00a80000>;
        };
        partition@0x00fa0000 {
            label = "spare";
            reg = <0x00fa0000 0x00000000>;
        };
    };
};
 
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/
&video_in_axi_vdma_0 {
   status = "disabled";
};
 
&video_out_axi_vdma_0 {
   status = "disabled";
};
 
&video_out_v_tc_0 {
    //xilinx-vtc: probe of 43c20000.v_tc failed with error -2
    status = "disabled";
};
 
&gpio0 {
    interrupt-controller;
    #interrupt-cells = <2>;
};
 
&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;
 
    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;
 
 
        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
 
            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
            };
 
        };
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
    };
 
};
 
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
 
&usb0 {
    usb-phy = <&usb_phy0>;
} ;
 
/*
* Sound configuration
*/
 
/{
    // Custom driver based on spdif-transmitter
    te_audio: dummy_codec_te {
        compatible = "te,te-audio";
        #sound-dai-cells = <0>;
    };
 
    // Simple Audio Card from AXI_I2S and custom XADC audio input and
    // PWM audio output cores
    sound {
        compatible = "simple-audio-card";
        simple-audio-card,name = "TE0726-PWM-Audio";
        simple-audio-card,format = "i2s";
        simple-audio-card,widgets =
            "Microphone", "In Jack",
            "Line", "Line In Jack",
            "Line", "Line Out Jack",
            "Headphone", "Out Jack";
 
        simple-audio-card,routing =
            "Out Jack", "te-out",
            "te-in", "In Jack";
 
        simple-audio-card,cpu {
            sound-dai = <&audio_axi_i2s_adi_0>;
        };
        simple-audio-card,codec {
            sound-dai = <&te_audio>;
        };
    };
};
 
&audio_axi_i2s_adi_0 {
    compatible = "adi,axi-i2s-1.00.a";
    reg = <0x43c00000 0x1000>;
    clocks = <&clkc 15>, <&clkc 18>; // FCLK_CLK0, FCLK_CLK3
    clock-names = "axi", "ref";
    dmas = <&dmac_s 0 &dmac_s 1>;
    dma-names = "tx", "rx";
    #sound-dai-cells = <0>;
};
 
/*
* We need to disable Linux XADC driver to use XADC for audio recording
*/
&adc {
    status = "disabled";
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_XILINX_GMII2RGMII=y

  • CONFIG_USB_USBNET=y

  • CONFIG_USB_NET_AX8817X=y

  • CONFIG_USB_NET_AX88179_178A=y

  • CONFIG_USB_NET_CDCETHER=y

  • # CONFIG_USB_NET_CDC_EEM is not set

  • CONFIG_USB_NET_CDC_NCM=y

  • # CONFIG_USB_NET_HUAWEI_CDC_NCM is not set

  • # CONFIG_USB_NET_CDC_MBIM is not set

  • # CONFIG_USB_NET_DM9601 is not set

  • # CONFIG_USB_NET_SR9700 is not set

  • # CONFIG_USB_NET_SR9800 is not set

  • # CONFIG_USB_NET_SMSC75XX is not set

  • CONFIG_USB_NET_SMSC95XX=y

  • # CONFIG_USB_NET_GL620A is not set

  • CONFIG_USB_NET_NET1080=y

  • # CONFIG_USB_NET_PLUSB is not set

  • # CONFIG_USB_NET_MCS7830 is not set

  • # CONFIG_USB_NET_RNDIS_HOST is not set

  • CONFIG_USB_NET_CDC_SUBSET_ENABLE=y

  • CONFIG_USB_NET_CDC_SUBSET=y

  • # CONFIG_USB_ALI_M5632 is not set

  • # CONFIG_USB_AN2720 is not set

  • CONFIG_USB_BELKIN=y

  • CONFIG_USB_ARMLINUX=y

  • # CONFIG_USB_EPSON2888 is not set

  • # CONFIG_USB_KC2190 is not set

  • CONFIG_USB_NET_ZAURUS=y

  • # CONFIG_USB_NET_CX82310_ETH is not set

  • # CONFIG_USB_NET_KALMIA is not set

  • # CONFIG_USB_NET_QMI_WWAN is not set

  • # CONFIG_USB_NET_INT51X1 is not set

  • # CONFIG_USB_SIERRA_NET is not set

  • # CONFIG_USB_VL600 is not set

  • # CONFIG_USB_NET_CH9200 is not set

  • CONFIG_USBIP_CORE=y

  • # CONFIG_USBIP_VHCI_HCD is not set

  • # CONFIG_USBIP_HOST is not set

  • # CONFIG_USBIP_VUDC is not set

  • # CONFIG_USBIP_DEBUG is not set

  • # CONFIG_FRAMEBUFFER_CONSOLE is not set
  • CONFIG_FB_SIMPLE=y

  • CONFIG_SND_SIMPLE_CARD_UTILS=y

  • CONFIG_SND_SIMPLE_CARD=y


Rootfs

File system will be generated with Debian script or Ubuntu script (mkdebian_Demo2_stretch.sh/mkubuntu_Demo2.sh)

Applications

Applications  will be generated with Debian script or Ubuntu script (mkdebian_Demo2_stretch.sh/mkubuntu_Demo2.sh)

Kernel Modules

te-audio-codec

Simple module stab to use audio interface. Will be installed with debian script

See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision

Authors

Description

  • typo
  • Programming issue note
2020-03-25v.7John Hartfiel
  • script update
2020-02-25v.6Mohsen Chamanbaz
  • add Ubuntu as root file system
  • documentation update
2020-02-21v.4Mohsen Chamanbaz
  • Vivado 2019.2 release
2020-01-13v.2Mohsen Chamanbaz
  • Vivado 2018.3 release
2018-12-19v.1John Hartfiel
  • Vivado 2018.2 release
--all
  • update documentation
Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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