Table of contents
Firmware for PCB CPLD with designator U14. CPLD Device in Chain: LCMX02-1200HC
- Power Management
- Boot Mode
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|BM0/MIO5||out||47||Boot Mode Pin|
|BM2/MIO4||out||48||Boot Mode Pin|
|BM3/MIO2||out||49||Boot Mode Pin|
|BOOTMODE||in||99||Boot Mode Pin from B2B / Used for UART as input to MIO9|
|CONFIGX||out||98||MIO8 to B2B / Used for UART as output from MIO8|
|DONE||in||34||FPGA Done Pin|
|EN_1.0V_MGT / EN_1V0_MGT||out||20||Power control|
|EN_1.2V_MGT / EN_1V2_MGT||out||18||Power control|
|ETH1_RESET33||in||43||ETH Reset from MIO7|
|I2C_SCL||in||58||I2C CLK / currently_not_used|
|I2C_SDA||in||57||I2C / currently_not_used|
|JTAGENB||in||82||Enable JTAG access to CPLD for Firmware update (zero: JTAG routed into CPLD logic, one: CPLD access)|
|LED1 / GLED||out||4||green LED D2|
|LED2 / RLED||out||3||red LED D1|
|M_TCK||in||91||CPLD JTAG B2B|
|M_TDI||in||94||CPLD JTAG B2B|
|M_TDO||out||95||CPLD JTAG B2B|
|M_TMS||in||90||CPLD JTAG B2B|
|MIO8||in||38||used UART RS activity|
|MIO9||out||39||User IO, connected to BOOTMODE Pin on B2B|
|N.C. / dummy||1||used as dummy output|
|OTG-RST33||in||45||OTG Reset from MIO0|
|PS_POR||out||37||PS_POR_B (Power On Reset)|
|PS_SRST||out||51||PS_SRST_B (PS Reset)|
|RESIN||in||97||Reset from B2B|
Used only for Firmware Update. Zynq has dedicated JTAG connection.
Power enables (EN_1V, EN_1V8, EN_3V3, EN_1V2_MGT, EN_1V0_MGT) are all enabled (constant 1).
Power goods (PG_1V, PG_1V5, PG_1V8, PG_3V3, PG_1V2_MGT, PG_1V0_MGT) are uses for System Reset and LED Monitoring.
Is set fix to QSPI (MIO(5:3) = 100)
PS_SRST is main power failed or user reset (RESIN).
ETH1_RESET is main power failed and ETH1_RESET33 and DONE.
OTG_RST is main power failed and ETH1_OTG_RST33 and DONE.
MMC_RST is main power or mgt power failed.
MIO8 is connected to CONFIGX.
BOOTMODE is connected to MIO9.
Red LED D1
|*ooooooo||1||PG_1V or PG_1V5 or PG_1V8 or PG_3V3 is zero||Main power problem|
|**oooooo||2||PG_1V2_MGT or PG_1V0_MGT is zero||MGT power Problem|
|***ooooo||3||B2B Main Reset is set (Zero)||User Main Reset|
|****oooo||4||FPG Done Pin is zero||FPGA part (PL) is not programmed|
Green LED D2
UART RX activity.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
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