Overview
This tutorial guides you from initaltest_board reference design for TE0821 SoM to custom extensible vitis platfom and then shows how to implement and run basic VADD example on 2cg module No. 1. Next, Vitis AI 2.0 BSP for large TE0821 4ev module No. 8 is created from module No. 1 files. Vitis-AI 2.0 dpu_trd example (ResNet50) running on DPU is compiled for the TE0821 4ev module No. 8.
Key Features
- Xilinx 2021.2 tools, Vivado 2021.2.1
- Vitis AI 2.0
- Vitis custom extensible platform for cg02_4gb module
- Vector addition on cg02_4gb module
- Creation of extensible platform for TE0821 ev04_4gb module by reuse of TE0821 cg02_4gb PetaLinux files
- Vitis-AI 2.0 dpu_trd example (ResNet50) with DPU on TE0821 ev04_4gb module
Requirements
| Type | Name | Version | Note |
|---|---|---|---|
| HW | TE0821 Module | -- | |
| HW | TE0706-03 Carrier | -- | TE0706-02 or TE0706-03 carrier can be used for Vitis AI 2.0 aplications without USB camera TE0706-03 carrier is required for Vitis AI 2.0 aplications with USB camera |
| Diverse Cable | USB, Power... | -- | -- |
| Virtual Maschine | Oracle, VMWare or MS WSL | -- | optional |
| OS | Linux | Xilinx Supported OS | running on VM or native |
| Reference Design | TE0821-test_board-vivado_2021.2-*.zip | build 20 or higher to match Vivado 2021.2.1 | Tutorial was created and tested with:
|
| SW | Vitis | 2021.2 | -- |
| SW | Vivado | 2021.2.1 | Vivado patch to 2021.2.1 is required by reference design package build 20 or higher |
| SW | Petalinux | 2021.2 | -- |
| SW | Putty | -- | -- |
| Repo | Vitis-AI | 2.0 | https://github.com/Xilinx/Vitis-AI/tree/2.0 |
On Win10 Pro PC, you can use: The presented extendible platform has been created on: Windows 10 Pro, ver. 21H2 OS build 19044.1889, VMware Workstation 16 Player (Version 16.2.4 build-20089737), Ubuntu 20.04 LTS Desktop 64-bit PC (AMD64) Only supported OS are selected Linux distributions. You will need either native or virtual PC with Linux distribution. Create new VM with Linux OS supported by Vitis 2021.2 tools. Use English as OS language for your Linux System. Keyboard language can be any language. In Ubuntu 20.04, open terminal and type command: Language is OK, if the command response starts with: In Ubuntu, set bash as terminal. Use of bash shell is required by Xilinx tools. On Ubuntu, install OpenCL Installable Client Driver Loader by executing: Download the Vitis Tools installer from the link below https://www.xilinx.com/support/download.html If Vitis 2021.2 is not installed, follow installation steps described in: After a successful installation of the Vitis 2021.2 and Vivado 2021.2 in /tools directory, a confirmation message is displayed, with a prompt to run the installLibs.sh script. Script location: In Ubuntu terminal, change directory to /tools/Vitis/2021.2/script and run the script using sudo privileges: The command installs a number of necessary packages for the Vitis 2021.2 tools based on the actual OS version of your Ubuntu system. If not applied before, apply the Xilinx y2k22_patch-1.2 to Vitis 2021.2 https://support.xilinx.com/s/article/76960?language=en_US In Ubuntu terminal, source paths to Vivado tools by executing Execute Vivado License Manager: From vlm, login to your Xilinx account by an www browser. In www browser, specify Vitis 2021.2 license. Select Linux target. Download xilinx license file and copy it into the directory of your choice. In vlm, select Load License -> Copy License The putty terminal can be used for Ethernet connected terminal. Putty supports keyboard, mouse and forwarding of X11 for Zynq Ultrascale+ applications designed for X11 desktop GUI. In Ubuntu terminal, execute: Exit from putty. Download the PetaLinux Tools installer from the link below https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html Install Petalinux 2021.2. Follow guideline described in: Before PetaLinux installation, check UG1144 chapter "PetaLinux Tools Installation Requirements" and install missing tool/libraries with help of script plnx-env-setup.sh attached to the Xilinx Answer Record 73296 - PetaLinux: How to install the required packages for the PetaLinux Build Host? The script detects whether the Host OS is a Ubuntu, RHEL, or CentOS Linux distribution and then automatically installs all of the required packages for the PetaLinux Build Host. The script requires root privileges. The script does not install the PetaLinux Tools. Command to run the script: Perform update of your PetaLinux and additional installation libraries. and follow the directions in the "Installing the PetaLinux Tool" section of (UG1144). To install petalinux do not start from shared folder, copy installer into your home directory. Source environmentPrepare Development Environment
Virtual Machine
https://www.virtualbox.org/
https://www.vmware.com/products/workstation-player/workstation-player-evaluation.html
https://wiki.trenz-electronic.de/display/PD/Xilinx+Tools+and+Win10+WSL
https://linuxconfig.org/Ubuntu-20-04-download Vitis/Vivado 2021.2 and creation of the extendible platform from ZIP archive has been also tested on:
Windows 11 Pro PC (upgrade from Windows 10 Pro, ver. 21H2 OS build 19044.1889)
VMware Workstation 16 Player (Version 16.2.4 build-20089737),
Ubuntu 20.04 LTS Desktop 64-bit PC (AMD64).
https://linuxconfig.org/Ubuntu-20-04-downloadLinux OS
Other languages may cause errors in PetaLinux build process. Set Language
$ locale
LANG=en_US.UTF-8
Set Bash as Terminal in Ubuntu
$ sudo dpkg-reconfigure dash shell
select: noThe Ubuntu 20.04 LTS terminal (selected as default installation) is dash.Install OpenCL Client Drivers
$ sudo apt-get install ocl-icd-libopencl1
$ sudo apt-get install opencl-headers
$ sudo apt-get install ocl-icd-opencl-dev
Software Installation
Vitis 2021.2
Download Vitis
Install Vitis
/tools/Vitis/2021.2/scripts/installLibs.sh
$ sudo installLibs.sh
Install y2k22_patch-1.2 to Vitis
Install License Supporting Vivado
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh
$ vlm
~/License/vitis_2021_2/Xilinx.licPutty
$ sudo apt install putty
To test the installation, execute putty application from Ubuntu terminal by:
$ putty &
Petalinux 2021.2
Download Petalinux
Install Required Libraries
https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-PetaLinux2021.2
https://www.xilinx.com/support/answers/73296.html
Use this page to download script: plnx-env-setup.sh
$ sudo ./plnx-env-setup.sh
$ sudo apt-get update
$ sudo apt-get install iproute2 gawk python3 python build-essential gcc git make net-tools libncurses5-dev tftpd zlib1g-dev libssl-dev flex bison libselinux1 gnupg wget git-core diffstat chrpath socat xterm autoconf libtool tar unzip texinfo zlib1g-dev gcc-multilib automake zlib1g:i386 screen pax gzip cpio python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 -y
Install Petalinux
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1144-petalinux-tools-reference-guide.pdf
$ mkdir -p ~/petalinux/2021.2
Copy petalinux-v2021.2-final-installer.run into ~/petalinux/2021.2
$ ./petalinux-v2020.2-final-installer.run
$ source ~/petalinux/2021.2/settings.sh
Prepare Reference Design for Extensible Custom Platform
Update Vivado Project for Extensible Platform
Trenz Electronic Scripts allows posibility change some setup via enviroment variables, which depends on the used OS and PC performace.
To improve performance on multicore CPU add global envirment on line 64:
export TE_RUNNING_JOBS=10
to /etc/bash.bashrc or local to design_basic_settings.sh
For othervariables see also:
In Ubuntu terminal, source paths to Vitis and Vivado tools by
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh
Download TE0821 test_board Linux Design file (see Reference Design download link on chapter Requirements) with pre-build files to
~/Downloads/TE0821-test_board-vivado_2021.2-build_20_20221107115647.zip
This TE0821test_board ZIP file contains bring-up scripts for creation of Petalinux for range of modules in zipped directory named “test_board”.
Unzip the file to directory:
~/work/TE0821_01_240
All supported modules are identified in file: ~/work/TE0821_01_240/test_board/board_files/TE0821_board_files.csv
We will select module 01 with name TE0821-01-2AE31KA, with device xczu2cg-sfvc784-1-e on TE0706-03 carrier board. We will use default clock 240 MHz.
That is why we name the package TE0821_01_240 and proposed to unzip the TE0821-test_board Linux Design files
TE0821-test_board-vivado_2021.2-build_20_20221107115647.zip
into the directory:
~/work/TE0821_01_240
In Ubuntu terminal, change directory to the test_board directory:
$ cd ~/work/TE0821_01_240/test_board
Setup thetest_board directory files for a Linux host machine.
In Ubuntu terminal, execute:
$ chmod ugo+rwx ./console/base_sh/*.sh $ chmod ugo+rwx ./_create_linux_setup.sh $ ./_create_linux_setup.sh
Select option (0) to open Selection Guide and press Enter
Select module variant 1 from the selection guide, press enter and agree selection
Module No. 01: TE0821-01-2AE31KA (zu02cg-1e-4gb) is selected.
Create Vivado Project by typing 1
Vivado project for module No. 01: TE0821-01-2AE31KA (zu02cg-1e-4gb) will be generated.
Selection Guide automatically modified ./design_basic_settings.sh with correct variant, so other provided bash files to recreate or open Vivado project again can be used later also.
In case of using selection guide, variant can be selected also manually:
The Vivado tool will be opened and Trenz Electronic HW project for the TE0821-test_board Linux Design, part 01 will be generated.
In Vivado window Sources, click on zusys_wrapper and next on zusys.bd to open the HW diagram in IP integrator:
It is possible to display diagram in separate window by clicking on float icon in upper right corner of the diagram.
Zynq Ultrascale+ block is configured for the Trenz TE0821-test_board Linux Design on the TE0706-03 carrier board.
This is starting point for the standard PetaLinux system supported by Trenz with steps for generation of the PetaLinux system. Parameters of this system and compilation steps are described on Trenz Wiki pages:
https://wiki.trenz-electronic.de/display/PD/TE0821+test_board
Follow steps described in these wiki pages if you would like to create fixed, not extensible Vitis platform.
The Extensible Vitis platform generation steps are described in next paragraphs.
Create Extensible Vitis platform
To implement hardware this tutorial offers two alternatives: Fast Track or Manual Track:
- Choose Fast Track to use TCL script to do the same modifications as in manual track case automatically,
- Select Manual Track path if you want to see all required hardware modifications required for custom platform.
Fast Track
Block Design of the Vivado project must be opened for this step. Copy following TCL Code to the TCL comand console of Vivado:
This script modifies the Initial platform Block design into the Extensible platform Block design and also defines define Platform Setup configuration.
In Vivado, open the design explorer and Platform description.
The fast track result is identical to the manually performed modifications described in next sections. In Vivado, save block design by clicking on icon “Save Block Design”.
Continue the design path with Validate Design.
Manual Track
In Vivado project, click in Flow Navigator on Settings. In opened Settings window, select General in Project Settings, select Project is an extensible Vitis platform. Click on OK.
IP Integrator of project set up as an extensible Vitis platform has an additional Platform Setup window.
Add multiple clocks and processor system reset IPs
In IP Integrator Diagram Window, right click, select Add IP and add Clocking Wizard IP clk_wiz_0. Double-click on the IP to Re-customize IP window. Select Output Clocks panel. Select four clocks with frequency 100, 200, 400 and 240 MHz.
100 MHz clock will serve as low speed clock.
200 MHz and 400 MHz clock will serve as clock for possible AI engine.
240 MHz clock will serve as the default extensible platform clock. By default, Vitis will compile HW IPs with this default clock.
Set reset type from the default Active High to Active Low.
Clik on OK to close the Re-customize IP window.
Disconnect clock network driven by output pl_clk0 of zynq_ultra_ps_e_0 from pl_clk0 and connect the complete clock network to output clk_out4 of clk_wiz_0. It will be driven by 240 MHz clock.
Connect input resetn of clk_wiz_0 with output pl_resetn0 of zynq_ultra_ps_e_0.
Connect input clk_in1 of clk_wiz_0 with output pl_clk0 of zynq_ultra_ps_e_0.
Modify lab tools frequency meter for 240 MHz clock.
Open the labtools_fmeter_0 and set the REF Clock in Hz to 240000000.
These modifications are made to support the axi-lite interface of an interrupt controller operating at 240 MHz clock, identical with the default extendable platform clock.
Add and connect Processor System Reset blocks for each generated clock.
Add four Processor System reser blocks and rename them proc_sys_reset_1, proc_sys_reset_2, proc_sys_reset_3 and proc_sys_reset_4.
Connect input slowest_sync_clk of proc_sys_reset_1 to clk_out1 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_2 to clk_out2 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_3 to clk_out3 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_4 to clk_out4 of clk_wiz_0.
Connect inputs ext_reset_in of proc_sys_reset_1, proc_sys_reset_2 proc_sys_reset_3 and proc_sys_reset_4 to output pl_resetn0 of zynq_ultra_ps_e_0.
Connect inputs dcm_locked of proc_sys_reset_1, proc_sys_reset_2 proc_sys_reset_3 and proc_sys_reset_4 to output locked of clk_wiz_0.
Platform Setup - clocks
Open Platform Setup window of IP Integrator to define Clocks. In Settings, select Clock.
In “Enabled” column select all four defined clocks clk_out1, clk_out2, clk_out3, clk_out4 of clk_wiz_0 block.
In “ID” column keep the default Clock ID: 1, 2, 3, 4
In “Is Default” column, select clk_out4 (with ID=4) as the default clock. One and only one clock must be selected as default clock.
Add, customize and connect the AXI Interrupt Controller
Add AXI Interrupt Controller IP axi_intc_0.
Double-click on axi_intc_0 to re-customize it.
In “Processor Interrupt Type and Connection” section select the “Interrupt Output Connection” from “Bus” to “Single”.
In “Peripherial Interrupt Type” section, change the “Interrupts Types Edge or Level” from AUTO to MANUAL. Change the corresponding value from 0xFFFFFFFF to 0x00000000.
Click on OK to accept these changes.
This re-configuration is manually setting all interrupts as level interrupts. With this setting, the PetaLinux automatically creates correct description of the interrupt controller in the device tree.
The Vitis extensible flow generates HW IP blocks with level interrupts.
The Vitis extensible flow generates HW IP blocks with level interrupts.
In case of user defined edge interrupts, the corresponding interrupt description will be added in an customised, interrupt controller description section of the user-defined device tree file
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
For the default extensible TE0821_01_240_pfm platform it is not needed.
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
For the default extensible TE0821_01_240_pfm platform it is not needed.
Connect interrupt controller clock input s_axi_aclk of axi_intc_0 to clock output dlk_out4 of clk_wiz_0. It is the default, 240 MHz clock of the extensible platform.
Connect interrupt controller input s_axi_aresetn of axi_intc_0 to output peripheral_aresetn[0:0] of proc_sys_reset_4 . It is the reset block for default, 240 MHz clock of the extensible platform.
Use the Run Connection Automation wizard to connect the axi lite interface of interrupt controller axi_intc_0 to zynq_ultra_ps_e_0. It is available in green line in top of the Diagram window.
In Run Connection Automaton window, click OK.
New AXI interconnect ps_8_axi_periph is created and related connections are generated.
Vitis extensible design flow will be expanding the AXI interconnect ps_8_axi_periph for interfacing and configuration of registers of generated HW IP blocks with the default extensible platform clock 240 MHz.
Modify the automatically generated reset network of AXI interconnect ps_8_axi_periph IP.
Disconnect input S00_ARESETN of ps_8_axi_periph from the network driven by output peripherial_aresetn[0:0] of proc_sys_reset_4 block.
Connect input S00_ARESETN of ps_8_axi_periph block with output interconnect_aresetn[0:0] of proc_sys_reset_4 block.
Disconnect input M00_ARESETN of ps_8_axi_periph block from the network driven by output peripherial_aresetn[0:0] of proc_sys_reset_4 block.
Connect input M00_ARESETN of ps_8_axi_periph to output interconnect_aresetn[0:0] of proc_sys_reset_4 block.
This modification will make the reset structure of the AXI interconnect ps_8_axi_periph block identical to the future extensions generated by the Vitis extensible design flow.
Double-click on zynq_ultra_ps_e_0 to re-customize it by enabling of an interrupt input pl_ps_irq0[0:0]. Click OK.
Connect the interrupt input pl_ps_irq0[0:0] of zynq_ultra_ps_e_0 block with output irq of axi_intc_0 block.
In Platform Setup, select “Interrupt” and enable intr in the “Enabled” column.
In Platform Setup, select AXI Port for zynq_ultra_ps_e_0:
Select M_AXI_HPM0_FPD and M_AXI_HPM1_FPD in column “Enabled”.
Select S_AXI_HPC0_FPD and S_AXI_HPC1_FPD in column “Enabled”.
For S_AXI_HPC0_FPD, change S_AXI_HPC to S_AXI_HP in column “Memport”.
For S_AXI_HPC1_FPD, change S_AXI_HPC to S_AXI_HP in column “Memport”.
Select S_AXI_HP0_FPD, S_AXI_HP1_FPD, S_AXI_HP2_FPD, S_AXI_HP3_FPD in column “Enabled”.
Type into the “sptag” column the names for these 6 interfaces so that they can be selected by v++ configuration during linking phase. HPC0, HPC1, HP0, HP1, HP2, HP3
In “Platform Setup”, select AXI Ports for ps8_0_axi_periph:
Select M01_AXI, M02_AXI, M03_AXI, M04_AXI, M05_AXI, M06_AXI and M07_AXI in column “Enabled”.
The modifications of the default design for the extensible platform are completed, now.
In Vivado, save block design by clicking on icon “Save Block Design”.
Continue the design path with Validate Design.
Validate Design
Results of HW creation via Manual Track or Fast Track are identical.
Open diagram by clicking on zusys.bd if not already open.
In Diagram window, validate design by clicking on “Validate Design” icon.
Received Critical Messages window indicates that input intr[0:0] of axi_intc_0 is not connected. This is expected. The Vitis extensible design flow will connect this input to interrupt outputs from generated HW IPs.
Click OK.
Known Issue: Sometimes an error in validation process may occur reporting create_pfm function is not known. Workaroud is to close vivado tool and reopen again to correclty load platform export API.
You can generate pdf of the block diagram by clicking to any place in diagram window and selecting “Save as PDF File”. Use the offered default file name:
~/work/TE0821_01_240/test_board/vivado/zusys.pdf
~/work/TE0821_01_240/test_board/vivado/zusys.pdf
Compile Created HW and Custom SW with Trenz Scripts
In Vivado Tcl Console, type following script and execute it by Enter. It will take some time to compile HW. HW design and to export the corresponding standard XSA package with included bitstream.
TE::hw_build_design -export_prebuilt
An archive for standard non-extensible system is created:
~/work/TE0821_01_240/test_board/vivado/test_board_2cg_1e_4gb.xsa
In Vivado Tcl Console, type the following script and execute it by Enter. It will take some time to compile.
TE::sw_run_vitis -all
After the script controlling SW compilation is finished, the Vitis SDK GUI is opened.
Close the Vitis “Welcome” page.
Compile the two included SW projects.
Standalone custom Vitis platform has been created and compiled.
The standalone custom Vitis platform includes Trenz Electronic custom first stage boot loader in folder zynqmp_fsbl. It includes SW extension specific for the Trenz module initialisation.
This custom zynqmp_fsbl project has been compiled into executable file fsbl.elf. It is located in: ~/work/TE0821_01_240/test_board/prebuilt/software/2cg_1e_4gb/fsbl.elf
This customised first stage boot loader is needed for the Vitis extensible platform.
We have used the standard Trenz scripts to generate it for next use in the extensible platform.
Exit the opened Vitis SDK project.
In Vivado top menu select File->Close Project to close project. Click OK.
In Vivado top menu select File->Exit to close Vivado. Click OK.
The exported Vitis Extensible Hardware platform named test_board_2cg_1e_4gb.xsa can be found in the vivado folder.
Copy Created Custom First Stage Boot Loader
Up to now,test_board directory has been used for all development.
~/work/TE0821_01_240/test_board
Create new folders:
~/work/TE0821_01_240/test_board_pfm/pfm/boot
~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir
Copy the recently created custom first stage boot loader executable file from
~/work/TE0821_01_240/test_board/prebuilt/software/2cg_1e_4gb/fsbl.elf
to
~/work/TE0821_01_240/test_board_pfm/pfm/boot/fsbl.elf
Building Platform OS and SDK
Configuration of the Default Trenz Petalinux for the Vitis Extensible Platform
Change directory to the default Trenz Petalinux folder
~/work/TE0821_01_240/test_board/os/petalinux
Source Vitis and Petalinux scripts to set environment for access to Vitis and PetaLinux tools.
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh $ source ~/petalinux/2021.2/settings.sh
Configure petalinux with the test_board_2cg_1e_4gb.xsa for the extensible design flow by executing:
$ petalinux-config --get-hw-description=~/work/TE0821_01_240/test_board/vivado
Select Exit->Yes to close this window.
Customize Root File System, Kernel, Device Tree and U-boot
In text editor, append definition of 32 interrupts by this text:
&amba { zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x0 0x10000>;
interrupt-parent = <&axi_intc_0>;
interrupts = <0 4>, <1 4>, <2 4>, <3 4>,
<4 4>, <5 4>, <6 4>, <7 4>,
<8 4>, <9 4>, <10 4>, <11 4>,
<12 4>, <13 4>, <14 4>, <15 4>,
<16 4>, <17 4>, <18 4>, <19 4>,
<20 4>, <21 4>, <22 4>, <23 4>,
<24 4>, <25 4>, <26 4>, <27 4>,
<28 4>, <29 4>, <30 4>, <31 4>;
};
};
to the system-user.dtsi file located in folder:
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/
Download the Vitis-AI 2.0 repository.
In browser, open page:
https://github.com/Xilinx/Vitis-AI/tree/2.0
Clik on green Code button and download Vitis-AI-2.0.zip file.
Unzip Vitis-AI-2.0.zip file to directory ~/Downloads/Vitis-AI.
Copy ~/Downloads/Vitis-AI to ~/vitis_ai_2_0
Delete Vitis-AI-2.0.zip, delete ~/Downloads/Vitis-AI, clean trash.
The directory ~/vitis_ai_2_0 contains the Vitis-AI 2.0 framework, now.
To install the Vitis-AI 2.0 version of shared libraries into rootfs (when generating system image by PetaLinux) we have to copy recepies recipes-vitis-ai to the Petalinux project :
Copy
~/vitis_ai_2_0/tools/Vitis-AI-Recipes/recipes-vitis-ai
to
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/In text editor, append these lines:
CONFIG_xrt CONFIG_xrt-dev CONFIG_zocl CONFIG_opencl-clhpp-dev CONFIG_opencl-headers-dev CONFIG_packagegroup-petalinux-opencv CONFIG_packagegroup-petalinux-opencv-dev CONFIG_dnf CONFIG_e2fsprogs-resize2fs CONFIG_parted CONFIG_resize-part CONFIG_packagegroup-petalinux-vitisai CONFIG_packagegroup-petalinux-self-hosted CONFIG_cmake CONFIG_packagegroup-petalinux-vitisai-dev CONFIG_mesa-megadriver CONFIG_packagegroup-petalinux-x11 CONFIG_packagegroup-petalinux-v4lutils CONFIG_packagegroup-petalinux-matchbox CONFIG_vitis-ai-library CONFIG_vitis-ai-library-dev CONFIG_vitis-ai-library-dbg
to the user-rootfsconfig file:
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/conf/user-rootfsconfig
xrt, xrt-dev and zocl are required for Vitis acceleration flow.
dnf is for package management.
parted, e2fsprogs-resize2fs and resize-part can be used for ext4 partition resize.
Other included packages serve for natively building Vitis AI applications on target board and for running Vitis-AI demo applications with GUI.
The last three packages will enable use of the Vitis-AI 2.0 recepies for installation of the correspoding Vitis-AI 2.0 libraries into rootfs of PetaLinux.
Enable all required packages in Petalinux configuration, from the Ubuntu terminal:
$ petalinux-config -c rootfs
Select all user packages by typing “y”. All packages will have to have an asterisk.
Still in the RootFS configuration window, go to root directory by select Exit once.
Enable OpenSSH and Disable Dropbear
Dropbear is the default SSH tool in Vitis Base Embedded Platform. If OpenSSH is used to replace Dropbear, the system could achieve faster data transmission speed over ssh. Created Vitis extensible platform applications may use remote display feature. Using of OpenSSH can improve the display experience.
Go to Image Features.
Disable ssh-server-dropbear and enable ssh-server-openssh and click Exit.
Go to Filesystem Packages->misc->packagegroup-core-ssh-dropbear and disable packagegroup-core-ssh-dropbear.
Go to Filesystem Packages level by Exit twice.
Go to console->network->openssh and enable openssh, openssh-sftp-server, openssh-sshd, openssh-scp.
Go to root level by selection of Exit four times.
Enable Package Management
Package management feature can allow the board to install and upgrade software packages on the fly.
In rootfs config go to Image Features and enable package-management and debug_tweaks option
Click OK, Exit twice and select Yes to save the changes.
Disable CPU IDLE in Kernel Config
CPU IDLE would cause processors get into IDLE state (WFI) when the processor is not in use. When JTAG is connected, the hardware server on host machine talks to the processor regularly. If it talks to a processor in IDLE status, the system will hang because of incomplete AXI transactions.
So, it is recommended to disable the CPU IDLE feature during project development phase.
It can be re-enabled after the design has completed to save power in final products.
Launch kernel config:
$ petalinux-config -c kernel
Ensure the following items are TURNED OFF by entering 'n' in the [ ] menu selection:
CPU Power Management->CPU Idle->CPU idle PM support
CPU Power Management->CPU Frequency scaling->CPU Frequency scaling
Exit and Yes to Save changes.
Add EXT4 rootfs Support
Let PetaLinux generate EXT4 rootfs. In terminal, execute:
$ petalinux-config
Go to Image Packaging Configuration.
Enter into Root File System Type
Select Root File System Type EXT4
Change the “Device node” of SD device from the default value
/dev/mmcblk0p2
to new value required for the TE0821 modules on TE0706-03 carrier:
/dev/mmcblk1p2
Exit and Yes to save changes.
Let Linux Use EXT4 rootfs During Boot
The setting of which rootfs to use during boot is controlled by bootargs. We would change bootargs settings to allow Linux to boot from EXT4 partition.
In terminal, execute:
$ petalinux-config
Change DTG settings->Kernel Bootargs->generate boot args automatically to NO.
Update User Set Kernel Bootargs to:
earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait cma=512M
Click OK, Exit three times and Save.
Build PetaLinux Image
In terminal, build the PetaLinux project by executing:
$ petalinux-build
The PetaLinux image files will be generated in the directory:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
Generation of PetaLinux takes some time and requires Ethernet connection and sufficient free disk space.
Create Petalinux SDK
The SDK is used by Vitis tool to cross compile applications for newly created platfom.
In terminal, execute:
$ petalinux-build --sdk
The generated sysroot package sdk.sh will be located in directory
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
Generation of SDK package takes some time and requires sufficient free disk space.
Time needed for these two steps depends also on number of allocated processor cores.
Copy Files for Extensible Platform
Copy these four files:
| Files | From | To |
|---|---|---|
| bl31.elf pmufw.elf system.dtb u-boot-dtb.elf | ~/work/TE0821_01_240/test_board/os/petalinux/images/linux | ~/work/TE0821_01_240/test_board_pfm/pfm/boot |
Rename the copied file u-boot-dtb.elf to u-boot.elf
The directory
~/work/TE0821_01_240/test_board_pfm/pfm/boot
contains these five files:
- bl31.elf
- fsbl.elf
- pmufw.elf
- system.dtb
- u-boot.elf
Copy files:
| Files | From | To |
|---|---|---|
| boot.scr system.dtb | ~/work/TE0821_01_240/test_board/os/petalinux/images/linux | ~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir |
Copy file:
| File | From | To |
|---|---|---|
| init.sh | ~/work/TE0821_01_240/test_board/misc/sd | ~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir |
init.sh is an place-holder for user defined bash code to be executed after the boot:
#!/bin/sh normal="\e[39m" lightred="\e[91m" lightgreen="\e[92m" green="\e[32m" yellow="\e[33m" cyan="\e[36m" red="\e[31m" magenta="\e[95m" echo -ne $lightred echo Load SD Init Script echo -ne $cyan echo User bash Code can be inserted here and put init.sh on SD echo -ne $normal
Create Extensible Platform zip File
Create new directory tree:
~/work/TE0821_01_240_move/test_board/os/petalinux/images
~/work/TE0821_01_240_move/test_board/Vivado
~/work/TE0821_01_240_move/test_board_pfm/pfm/boot ~/work/TE0821_01_240_move/test_board_pfm/pfm/sd_dir
Copy all files from the directory:
| Files | Source | Destination |
|---|---|---|
| all | ~/work/TE0821_01_240/test_board/os/petalinux/images | ~/work/TE0821_01_240_move/test_board/os/petalinux/images |
| all | ~/work/TE0821_01_240/test_board_pfm/pfm/boot | ~/work/TE0821_01_240_move/test_board_pfm/pfm/boot |
| all | ~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir | ~/work/TE0821_01_240_move/test_board_pfm/pfm/sd_dir |
| test_board_2cg_1e_4gb.xsa | ~/work/TE0821_01_240/test_board/Vivado/test_board_2cg_1e_4gb.xsa | ~/work/TE0821_01_240_move/test_board/Vivado/test_board_2cg_1e_4gb.xsa |
Zip the directory
~/work/TE0821_01_240_move
into ZIP archive:
~/work/TE0821_01_240_move.zip
The archive TE0821_01_240_move.zip can be used to create extensible platform on the same or on an another PC with installed Ubuntu 20.04 and Vitis tools, with or without installed Petalinux. The archive includes all needed components, including the Xilinx xrt library and the script sdk.sh serving for generation of the sysroot .
The zip archive has size approximately 5.3 GB.
Move the TE0821_01_240_move.zip file to an PC disk drive.
Delete:
~/work/TE0821_01_240_move
~/work/TE0821_01_240_move.zip
Clean the Ubuntu Trash.
Generation of SYSROOT
This part of development can be direct continuation of the previous Petalinux configuration and compilation steps.
Alternatively, it is also possible to implement all next steps on an Ubuntu 20.04 without installed PetaLinux Only the Ubuntu 20.04 and Vitis/Vivado installation is needed.
All required files created in the PetaLinux for the specific module (24) are present in the archive: TE0821_01_240_move.zip
In this case, unzip the archive to the directory:
~/work/TE0821_01_240_move
and copy all content of directories to
~/work/TE0821_01_240
Delete the TE0821_01_240_move.zip file and the ~/work/TE0821_01_240_move directory to save filesystem space.
All required files created in the PetaLinux for the specific module (24) are present in the archive: TE0821_01_240_move.zip
In this case, unzip the archive to the directory:
~/work/TE0821_01_240_move
and copy all content of directories to
~/work/TE0821_01_240
Delete the TE0821_01_240_move.zip file and the ~/work/TE0821_01_240_move directory to save filesystem space.
In Ubuntu terminal, change the working directory to:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
In Ubuntu terminal, execute script enabling access to Vitis 2021 tools.
Execution of script serving for setting up PetaLinux environment is not necessary:
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh
In Ubuntu terminal, execute script
$ ./sdk.sh -d ~/work/TE0821_01_240/test_board_pfm
SYSROOT directories and files for PC and for Zynq Ultrascale+ will be created in:
~/work/TE0821_01_240/test_board_pfm/sysroots/x86_64-petalinux-linux
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
Once created, do not move these sysroot directories (due to some internally created paths).
Generation of Extensible Platform for Vitis
In Ubuntu terminal, change the working directory to:
~/work/TE0821_01_240/test_board_pfm
Start the Vitis tool by executing
$ vitis &
In Vitis “Launcher”, set the workspace for the extensible platform compilation:
~/work/TE0821_01_240/test_board_pfm
Click on “Launch” to launch Vitis
Close Welcome page.
In Vitis, select in the main menu: File -> New -> Platform Project
Type name of the extensible platform: TE0821_01_240_pfm. Click Next.
Choose for hardware specification for the platform file:
~/work/TE0821_01_240/test_board/vivado/test_board_2cg_1e_4gb.xsa
In “Software specification” select: linux
In “Boot Components” unselect Generate boot components
(these components have been already generated by Vivado and PetaLinux design flow)
New window TE0821_01_240_pfm is opened.
Click on linux on psu_cortex53 to open window Domain: linux_domain
In “Description”: write xrt
In “Bif File” find and select the pre-defied option: Generate Bif
In “Boot Components Directory” select:
~/work/TE0821_01_240/test_board_pfm/pfm/boot
In “FAT32 Partition Directory” select:
~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir
In Vitis IDE “Explorer” section, click on TE0821_01_240_pfm to highlight it.
Right-click on the highlighted TE0821_01_240_pfm and select build project in the open submenu. Platform is compiled in few seconds.
Close the Vitis tool by selection: File -> Exit.
Vitis extensible platform TE0821_01_240_pfm has been created in the directory:
~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm
Platform Usage
Test 1: Read Platform Info
With Vitis environment setup, platforminfo tool can report XPFM platform information.
platforminfo ~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm/TE0821_01_240_pfm.xpfm
Detailed listing from platforminfo utility
==========================
Basic Platform Information
==========================
Platform: te0821_01_240_pfm
File: /home/devel/work/te0821_01_240/test_board_pfm/te0821_01_240_pfm/export/te0821_01_240_pfm/te0821_01_240_pfm.xpfm
Description:
te0821_01_240_pfm
=====================================
Hardware Platform (Shell) Information
=====================================
Vendor: vendor
Board: zusys
Name: zusys
Version: 1.0
Generated Version: 2021.2.1
Hardware: 1
Software Emulation: 1
Hardware Emulation: 1
Hardware Emulation Platform: 0
FPGA Family: zynquplus
FPGA Device: xczu2cg
Board Vendor: trenz.biz
Board Name: trenz.biz:te0821_2cg_1e:3.0
Board Part: xczu2cg-sfvc784-1-e
=================
Clock Information
=================
Default Clock Index: 4
Clock Index: 1
Frequency: 100.000000
Clock Index: 2
Frequency: 200.000000
Clock Index: 3
Frequency: 400.000000
Clock Index: 4
Frequency: 240.000000
==================
Memory Information
==================
Bus SP Tag: HP0
Bus SP Tag: HP1
Bus SP Tag: HP2
Bus SP Tag: HP3
Bus SP Tag: HPC0
Bus SP Tag: HPC1
=============================
Software Platform Information
=============================
Number of Runtimes: 1
Default System Configuration: te0821_01_240_pfm
System Configurations:
System Config Name: te0821_01_240_pfm
System Config Description: te0821_01_240_pfm
System Config Default Processor Group: linux_domain
System Config Default Boot Image: standard
System Config Is QEMU Supported: 1
System Config Processor Groups:
Processor Group Name: linux on psu_cortexa53
Processor Group CPU Type: cortex-a53
Processor Group OS Name: linux
System Config Boot Images:
Boot Image Name: standard
Boot Image Type:
Boot Image BIF: te0821_01_240_pfm/boot/linux.bif
Boot Image Data: te0821_01_240_pfm/linux_domain/image
Boot Image Boot Mode: sd
Boot Image RootFileSystem:
Boot Image Mount Path: /mnt
Boot Image Read Me: te0821_01_240_pfm/boot/generic.readme
Boot Image QEMU Args: te0821_01_240_pfm/qemu/pmu_args.txt:te0821_01_240_pfm/qemu/qemu_args.txt
Boot Image QEMU Boot:
Boot Image QEMU Dev Tree:
Supported Runtimes:
Runtime: OpenCL
Test 2: Run Vector Addition Example
Create new directorytest_board_test_vadd to test Vitis extendable flow example “vector addition”
~/work/TE0821_01_240/test_board_test_vadd
Current directory structure:
~/work/TE0821_01_240/test_board
~/work/TE0821_01_240/test_board_pfm
~/work/TE0821_01_240/test_board_test_vadd
Change working directory:
$cd ~/work/TE0821_01_240/test_board_test_vadd
In Ubuntu terminal, start Vitis by:
$ vitis &
In Vitis IDE Launcher, select your working directory
~/work/TE0821_01_240/test_board_test_vadd
Click on Launch to launch Vitis.
Select File -> New -> Application project. Click Next.
Skip welcome page if shown.
Click on “+ Add” icon and select the custom extensible platform TE0821_01_240_pfm[custom] in the directory:
~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm
We can see available PL clocks and frequencies.
PL4 with 240 MHz clock is has been set as default in the platform creation process.
Click Next.
In “Application Project Details” window type into Application project name: test_vadd
Click Next.
In “Domain window” type (or select by browse):
“Sysroot path”:
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
“Root FS”:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/rootfs.ext4
“Kernel Image”:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/Image
Click Next.
In “Templates window”, if not done before, update “Vitis IDE Examples” and “Vitis IDE Libraries”.
Select Host Examples
In “Find”, type: “vector add” to search for the “Vector Addition” example.
Select: “Vector Addition”
Click Finish
New project template is created.
In test_vadd window menu “Active build configuration” switch from “SW Emulation” to “Hardware”.
In “Explorer” section of Vitis IDE, click on: test_vadd_system[TE0821_01_240_pfm] to select it.
Right Click on: test_vadd_system[TE0821_01_240_pfm] and select in the opened sub-menu:
Build project
Vitis will compile:
In test_vadd_kernels subproject, compile the krnl_vadd from C++ SW to HDL HW IP source code
In test_vadd_system_hw_link subproject, compile the krnl_vadd HDL together with TE0821_01_240_pfm into new, extended HW design with new accelerated (krnl_vadd) will run on the default 240 MHz clock. This step can take some time.
In test_vadd subproject, compile the vadd.cpp application example.
Run Compiled Example Application
The sd_card.img file is output of the compilation and packing by Vitis. It is located in directory:
~/work/TE0821_01_240/test_board_test_vadd/test_vadd_system/Hardware/package/sd_card.img
Write the sd card image from the sd_card.img file to SD card.
In Windows Pro 10 (or Windows 11 Pro) PC, inst all program Win32DiskImager for this task. Win32 Disk Imager can write raw disk image to removable devices.
https://win32diskimager.org/
https://win32diskimager.org/
Insert the SD card to the TE0706-03 carrier board.
Connect PC USB terminal (115200 bps) card to the TE0706-03 carrier board.
Connect USB Keyboard and USB Mouse to the TE0706-03 carrier board.
Connect Ethernet cable to the TE0706-03 carrier board.
Power on the TE0706-03 carrier board.
In PC, find the assigned serial line COM port number for the USB terminal. In case of Win 10 use device manager.
In PC, open serial line terminal with the assigned COM port number. Speed 115200 bps.
Connect Monitor to the Display Port connector of the TE0706-03 carrier board.
On TE0706-03, press button S1 to start the system (press the button for cca. 1 sec. ).
(FMC fan starts to rotate, USB terminal starts to display booting information)
Display Port Monitor indicates text “Please wait: Booting…” (white text, black background).
X11 screen opens on Display port.
Mouse and keyboard connected to the TE0706-03 carrier board can be used.
Click on “Terminal” icon (A Unicode capable rxvt)
Terminal opens as an X11 graphic window.
In terminal, use keyboard connected to the TE0706-03 carrier board and type:
sh-5.0# cd /media/sd-mmcblk1p1/ sh-5.0# ./test_vadd krnl_vadd.xclbin
The application test_vadd should run with this output:
sh-5.0# cd /media/sd-mmcblk1p1/ sh-5.0# ./test_vadd krnl_vadd.xclbin INFO: Reading krnl_vadd.xclbin Loading: 'krnl_vadd.xclbin' Trying to program device[0]: edge Device[0]: program successful! TEST PASSED sh-5.0#
The Vitis application has been compiled to HW and evaluated on custom system
with extensible custom TE0821_01_240_pfm platform.
Close the rxvt terminal emulator by click ”x” icon (in the upper right corner) or by typing:
# exit
In X11, click on ”Shutdown” icon to close down safely.
System is halted. Messages relate to halt of the system can be seen on the USB terminal).
The SD card can be safely removed from the TE0706-03 carrier board, now.
The TE0706-03 carrier board can be disconnected from power.
The TE0706-03 carrier with TE0821-01-2AE31KA module No. 1 with device xczu2cg-sfvc784-1-e and 4GB memory is running the PetaLinux OS and drives simple version of an X11 GUI on a PC with Ubuntu 20.04 on virtual machine. Application test_vadd is executed in remote X11 terminal.
- Petalinux boot,
- ifconfig to find assigned Ethernet address,
- test_vadd example executed to test the kernel execution,
- halt to proper terminate OS.
Test 3: Create Vitis AI 2.0 BSP for large TE0821 module No. 8
Module No. 1: TE0821-01-2AE31KA with zu02cg-1e-4gb device has small PL part for implementation of the full size Vitis AI 2.0 DPU unit.
We will demonstrate how to implement the DPU unit and the DPU_TRD examole example on TE0821 module No. 8: TE0821-01-4DE31FL with xczu4ev-sfvc784-1-e device and 4gb memory.
Reuse of Petalinux files created for module No. 1.
First, we have to create new HW BSP for module No. 8.
Follow steps described for module No. 1: TE0821-01-2AE31KA with xczu2cg-sfvc784-1-e device and 4gb memory.
Extract bring up files to prepare HW design for module No. 8 in irectory:
~/work/TE0821_08_240/test_board
Expand PL HW design for module No. 8 up to the creation of .xsa archive in:
~/work/TE0821_08_240/test_board/vivado/test_board_4ev_1e_4gb.xsa
and fsbl.elf file in:
~/work/TE0821_08_240/test_board/prebuild/software/fsbl.elf
Follow same steps as described initially for Module No. 1.
Copy files (allready created for Module No. 1 extensible platform) to module No. 8 extensible platform directories:
~/work/TE0821_08_240/test_board_pfm/pfm/boot
~/work/TE0821_08_240/test_board_pfm/pfm/sd-dir
Copy these four files:
| Files | From | To |
|---|---|---|
| bl31.elf pmufw.elf system.dtb u-boot.elf | ~/work/TE0821_01_240/test_board_pfm/pfm/boot | ~/work/TE0821_08_240/test_board_pfm/pfm/boot |
Copy fsbl.elf file created for module No. 8 from:
~/work/TE0821_08_240/test_board/prebuild/software/fsbl.elf
to:
~/work/TE0821_08_240/test_board_pfm/pfm/boot/fsbl.elf
The directory
~/work/TE0821_08_240/test_board_pfm/pfm/boot
contains these five files, now:
- bl31.elf
- fsbl.elf
- pmufw.elf
- system.dtb
- u-boot.elf
Copy 3 files (created allready for Module No. 1) :
| Files | From | To |
|---|---|---|
boot.scr | ~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir | ~/work/TE0821_08_240/test_board_pfm/pfm/sd_dir |
Generation of Extensible Platform for module No. 8.
In Ubuntu terminal, change the working directory to:
~/work/TE0821_08_240/test_board_pfm
Start the Vitis tool by executing
$ vitis &
In Vitis “Launcher”, set the workspace for the extensible platform compilation:
~/work/TE0821_08_240/test_board_pfm
Click on “Launch” to launch Vitis
Close Welcome page.
In Vitis, select in the main menu: File -> New -> Platform Project
Type name of the extensible platform: TE0821_08_240_pfm. Click Next.
Choose for hardware specification for the platform file:
~/work/TE0821_08_240/test_board/vivado/test_board_4ev_1e_4gb.xsa
In “Software specification” select: linux
In “Boot Components” unselect Generate boot components
(these components have been already generated by Vivado and PetaLinux design flow)
New window TE0821_08_240_pfm is opened.
Click on linux on psu_cortex53 to open window Domain: linux_domain
In “Description”: write xrt
In “Bif File” find and select the pre-defied option: Generate Bif
In “Boot Components Directory” select:
~/work/TE0821_08_240/test_board_pfm/pfm/boot
In “FAT32 Partition Directory” select:
~/work/TE0821_08_240/test_board_pfm/pfm/sd_dir
In Vitis IDE “Explorer” section, click on TE0821_08_240_pfm to highlight it.
Right-click on the highlighted TE0821_08_240_pfm and select build project in the open submenu. Platform is compiled in few seconds.
Close the Vitis tool by selection: File -> Exit.
Vits extensible platform TE0821_08_240_pfm has been created in the directory:
~/work/TE0821_08_240/test_board_pfm/TE0821_08_240_pfm/export/TE0821_08_240_pfm
The Vitis AI 2.0 HW platform for module No. 8 is created now.
Test 4: Vitis-AI Demo test on larger TE0821 module
This test implements simple AI demo to verify DPU integration to our custom extensible platform. This tutorial follows Xilix Vitis Tutorial for zcu104 with necessary fixes and customizations required for our case.
Create and Build Vitis Design
The Vitis AI Design with DPU will be gemerated by these steps:
Create new directorytest_board_dpu_trd to test Vitis extendable flow example “dpu trd”
~/work/TE0821_08_240/test_board_dpu_trd
Current directory structure:
~/work/TE0821_01_240/test_board
~/work/TE0821_01_240/test_board_pfm
~/work/TE0821_01_240/test_board_test_vadd
~/work/TE0821_08_240/test_board
~/work/TE0821_08_240/test_board_pfm
~/work/TE0821_08_240/test_board_dpu_trd
Change working directory:
$cd ~/work/TE0821_08_240/test_board_dpu_trd
In Ubuntu terminal, start Vitis by:
$ vitis &
In Vitis IDE Launcher, select your working directory
~/work/TE0821_08_240/test_board_dpu_trd
Click on Launch to start Vitis.
Add Vitis-AI Repository to Vitis
Open menu Window → Preferences
Go to Library Repository tab
Add Vitis-AI by clicking Add button and fill the form as shown below, use absolute path to your home folder in field "Location":
Click Apply and Close.
Field "Location" says that the Vitis-AI repository from github has been cloned into ~/vitis_ai_2_0 folder, already in the stage of Petalinux configuration. It is the same Vitis-AI 2.0 package downloaded from the branch 2.0. Use the absolute path to your home directory. It depends on the user name. The user name in the figure is "devel". Replace it by your user name.
Correctly added library appears in Libraries:
Open menu Xilinx → Libraries...
You can find there just added Vitis-AI library marked as "Installed".
Create a Vitis-AI Design for our TE0821_01_240 custom platform
Select File -> New -> Application project. Click Next.
Skip welcome page if it is shown.
Click on “+ Add” icon and select the custom extensible platform TE0821_08_240_pfm[custom] in the directory:
~/work/TE0821_08_240/test_board_pfm/TE0821_08_240_pfm/export/TE0821_08_240_pfm
Click Next.
In “Application Project Details” window type into Application project name: dpu_trd
Click Next.
In “Domain window” type (or select by browse):
“Sysroot path” (Sysroot of module No. 1 is reused):
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
“Root FS” (FS of module No. 1 is reused):
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/rootfs.ext4
“Kernel Image” (Kernel Image of module No. 1 is reused):
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/Image
Click Next.
In dsa folder, select: “DPU Kernel (RTL Kernel)”
Click Finish
New project template is created.
In dpu_trd window menu “Active build configuration” switch from “SW Emulation” to “Hardware”.
File dpu_conf.vh located at dpu_trd_kernels/src/prj/Vitis directory contains DPU configuration.
Open file dpu_conf.vh and change in line 37:
`define URAM_DISABLE
to
`define URAM_ENABLE
and save modified file.
This modification is necessary for succsessfull implementation of the DPU on the zcu04-ev module with internal memories implemented in URAMs.
Go to dpu_trd_system_hw_link and double click on dpu_trd_system_hw_link.prj.
Remove sfm_xrt_top kernel from binary container by right clicking on it and choosing remove.
Reduce number of DPU kernels to one.
Configure connection of DPU kernels
On the same tab right click on dpu and choose Edit V++ Options
Click "..." button on the line of V++ Configuration Settings and modify configuration as follows:
[clock] freqHz=200000000:DPUCZDX8G_1.aclk freqHz=400000000:DPUCZDX8G_1.ap_clk_2 [connectivity] sp=DPUCZDX8G_1.M_AXI_GP0:HPC0 sp=DPUCZDX8G_1.M_AXI_HP0:HP0 sp=DPUCZDX8G_1.M_AXI_HP2:HP1
Update packaging to add dependencies into SD Card
Create a new folder img in your project in dpu_trd/src/app
Download image from provided link and place it to newly created folder dpu_trd/src/app/img.
Double click dpu_trd_system.sprj
Click "..." button on Packaging options
Enter "--package.sd_dir=../../dpu_trd/src/app"
Click OK.
Build DPU_TRD application
In “Explorer” section of Vitis IDE, click on: dpu_trd_system[TE0821_08_240_pfm] to select it.
Right Click on: dpu_trd_system[TE0821_08_240_pfm] and select in the opened sub-menu:
Build project
Run DPU_TRD on Board
Write sd_card.img to SD card using SD card reader.
The sd_card.img file is output of the compilation and packing by Vitis. It is located in directory:
~/work/TE0821_08_240/test_board_dpu_trd/dpu_trd_system/Hardware/package/
In Windows Pro 10 (or Windows 11 Pro) PC, inst all program Win32DiskImager for this task. Win32 Disk Imager can write raw disk image to removable devices.
https://win32diskimager.org/
https://win32diskimager.org/
Boot the board and open terminal on the board either by connecting serial console connection, or by opening ethernet connection to ssh server on the board, or by opening terminal directly using window manager on board. Continue using the embedded board terminal.
Detailed guide how to run embedded board and connect to it can be found in Run Compiled Example Application for Vector Addition.
Check ext4 partition size by:
root@petalinux:~# cd / root@petalinux:~# df . Filesystem 1K-blocks Used Available Use% Mounted on /dev/root 564048 398340 122364 77% /
Resize partition
root@petalinux:~# resize-part /dev/mmcblk1p2 /dev/mmcblk1p2 Warning: Partition /dev/mmcblk1p2 is being used. Are you sure you want to continue? parted: invalid token: 100% Yes/No? yes End? [2147MB]? 100% Information: You may need to update /etc/fstab. resize2fs 1.45.3 (14-Jul-2019) Filesystem at /dev/mmcblk1p2 is mounted on /media/sd-mmcblk1p2; o[ 72.751329] EXT4-fs (mmcblk1p2): resizing filesystem from 154804 to 1695488 blocks n-line resizing required old_desc_blocks = 1, new_desc_blocks = 1 [ 75.325525] EXT4-fs (mmcblk1p2): resized filesystem to 1695488 The filesystem on /dev/mmcblk1p2 is now 1695488 (4k) blocks long.
Check ext4 partition size again, you should see:
root@petalinux:~# df . -h Filesystem Size Used Available Use% Mounted on /dev/root 6.1G 390.8M 5.4G 7% /
The available size would be different according to your SD card size.
Copy dependencies to home folder:
# Libraries root@petalinux:~# cp -r /mnt/sd-mmcblk1p1/app/samples/ ~ # Model root@petalinux:~# cp /mnt/sd-mmcblk1p1/app/model/resnet50.xmodel ~ # Host app root@petalinux:~# cp /mnt/sd-mmcblk1p1/dpu_trd ~ # Images to test root@petalinux:~# cp /mnt/sd-mmcblk1p1/app/img/*.JPEG ~
Run the application from /home/root folder and you can observe that "bell pepper" receives highest score.
root@petalinux:~# env XLNX_VART_FIRMWARE=/mnt/sd-mmcblk1p1/dpu.xclbin ./dpu_trd bellpeppe-994958.JPEG score[945] = 0.992235 text: bell pepper, score[941] = 0.00315807 text: acorn squash, score[943] = 0.00191546 text: cucumber, cuke, score[939] = 0.000904801 text: zucchini, courgette, score[949] = 0.00054879 text: strawberry,
The resnet50 is trained for recognition of 1000 different objects.
The test board application reads the input figure and call the DPU with 8bit coefficients of the ResNet50 network.
The "bell pepper" object is recognised with high probability.
On board compilation of Vitis AI 2.0 demo
The application dpu_trd can be recompiled directly on the test board.
chmod 777 ./build.sh ./build.sh Opencv4 OpenCV - Open Source Computer Vision Library root@petalinux:~# env XLNX_VART_FIRMWARE=/mnt/sd-mmcblk1p1/dpu.xclbin ./a.out bellpeppe-994958.JPEG score[945] = 0.992235 text: bell pepper, score[941] = 0.00315807 text: acorn squash, score[943] = 0.00191546 text: cucumber, cuke, score[939] = 0.000904801 text: zucchini, courgette, score[949] = 0.00054879 text: strawberry,
The result of on compilation on test board is aplication a.out.
It provides identical results to the dpu_trd application compiled in Vitis in the PC Ubuntu Vitis AI environment.
Only the C++ SW part of the application can be compiled on the test board. The HW acceleration part (the dpu kernel)
has to be compiled in Ubuntu Vitis AI 2.0 framework (with Vivado).
Additional Vitis AI 2.0 demos
Many additional demos from the Vitis AI 2.0 library can be compiled on the test board and executed on the test board with identical dpu.
Vitis AI 2.0 demos work in several modes:
- From a image stored in a file with output in form of text to console or image displayed on the X11 desktop.
- From sequence of image stored in several files with output in form of text to console or images displayed on the X11 deskto
- From USB 2/3 www camera input video with output in form video displayed on the X11 remote desktop.
Use of USB 2/3 www camera input video requires the test board te0706-03 for correct recognition of the USB www camera.
Starting point for exploration of these Vitis AI 2.0 examples is this Xilinx www page.
Vitis AI 2.0 is Here! (xilinx.com)
TE0820 modules with smaller programmable logic area without URAMs (all xzcu2 and zxcu3 modules ) with 2GB of DDR4 are supported only for the extensible flow applications like the test_vadd demo.
Starting point for exploration of Vitis acceleration flow is Vitis Accel Examples' Repository (project templates are already downloaded in Vitis):
GitHub - Xilinx/Vitis_Accel_Examples at 2021.2
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