Overview
CPLD Device with designator U46: 10M08SAU169
For use with the TEBT0865-01 carrier board a small hardware patch on TEBT0865-01 is required.
PCN-20240909 TE0865-02 CPLD Firmware Update / TEBT0865-01 Hardware Patch
Feature Summary
- JTAG_UART
- Power management
- Reset
- I2C
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | I/O Bank | Pullup/Down | I/O Standard | Current Strength | Description |
|---|---|---|---|---|---|---|---|
| JTAGEN | in | E5 | -- | 3.3V | fixed to 3.3V | ||
| TCK_MAX10 | in | G2 | -- | 2.5V (default) | 12mA (default) | JTAG | |
| TMS_MAX10 | in | G1 | -- | 2.5V (default) | 12mA (default) | JTAG | |
| TDO_MAX10 | out | F6 | -- | 2.5V (default) | 12mA (default) | JTAG | |
| TDI_MAX10 | in | F5 | -- | 2.5V (default) | 12mA (default) | JTAG | |
| PG_1V2_PL_DDR | in | H5 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| PG_VCCINT | in | N3 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| LTM_FAULT | in | N2 | 2 | 3.3V LVCMOS | 2mA (default) |
| |
| M_SDA | inout | M3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
|
| EN_SOM | in | K1 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| SC_EXT_3 | in | L2 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
|
| EN_VTT_PL_DDR | out | J2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_2V5_PL_DDR | out | J1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V2_PL_DDR | out | H4 | 2 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V8_PS_AUX | out | M2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
|
| PG_SOM | out | M1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
|
| SC_EXT_2 | out | L3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
|
| MR | inout | K2 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| SMB_ALERTn | in | L4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
|
| PG_2V5_PL_DDR | in | L5 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| M_SCL | inout | M4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
|
| nRST_SYS | out | K5 | 3 | 3.3V LVCMOS | 2mA (default) |
| |
PG_1V2_PS_DDR | in | M7 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_0V9_GTH_AVCC | in | N6 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_0V9_GTY_AVCC | in | N8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_1V8_PS_GTR_AVTT | in | M9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_1V8 | in | M8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| PG_1V2_GTY_AVTT | in | N9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| M_INT | in | L11 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
|
| PG_0V85_PS_GTR_AVCC | in | K8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| PG_2V3 | in | N12 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
| EN_LTM_RUNP | out | M5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_0V9_GTH_AVCC | out | N5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_0V9_GTY_AVCC | out | N4 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_3V3_SW | out | N7 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V2_PS_PLL | out | J6 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_2V5_PS_DDR | out | M13 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V2_GTY_AVTT | out | N10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V8_VCC_ADC | out | M11 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_VTT_PS_DDR | out | J8 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V8 | out | L10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
| EN_1V8_GTY_AUX | out | M10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
|
PG_3V3_SW | in | J9 | 5 | -- | 3.3V LVCMOS | 2mA (default) |
|
PG_1V2_GTH_AVTT | in | H9 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_1V8_AUX | in | G12 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
PG_2V5_PS_DDR | in | L13 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
EN_1V8_PS_GTR_AVTT | out | K10 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_1V8_GTH_AUX | out | K11 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_1V8_AUX | out | K12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_1V2_GTH_AVTT | out | J12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_1V2_PS_DDR | out | J13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_0V85_PS_GTR_AVCC | out | H13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
EN_VCCINT | inout | H8 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
|
EN_2V3 | out | G13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
|
Functional Description
JTAG
JTAG access to Intel MAX 10 is available through B2B connector J2.
| JTAG Signal | B2B Connector |
|---|---|
| JTAGEN | Pulled Up |
| TCK_MAX10 | J2B- D56 |
| TDI_MAX10 | J2B- D59 |
| TDO_MAX10 | J2B- D58 |
| TMS_MAX10 | J2B- D57 |
Power
All power regulators are controlled by the power sequencer core from Intel. It enables and discharges the power regulators and monitors the power good signals. As the power good inputs of the power sequencer are very sensitive, all power good inputs were debounced. https://github.com/intel/multi_power_sequencer
The power-up sequence corresponds to AMD's recommendations and is shown in the table below:
| Power Group | Power enable signal (CPLD output signal) | Power good signal (CPLD input signal) | Sequencer Delay1 (PG to next OE) | Qualification Window2 (OE to PG) | Notes |
|---|---|---|---|---|---|
0 | -- | EN_SOM | 10µs | 200ms |
|
1 | EN_VCCINT | PG_VCCINT |
10µs
|
200ms | -- |
EN_2V3 | PG_2V3 | -- | |||
EN_3V3_SW | PG_3V3_SW | +3.3V_SW output signal from U52 | |||
2 | EN_1V8 | PG_1V8 |
10µs
|
200ms
| -- |
EN_1V8_AUX | PG_1V8_AUX | -- | |||
EN_1V8_PS_AUX | -- | -- | |||
EN_1V2_PS_PLL | -- | -- | |||
EN_0V9_GTH_AVCC | PG_0V9_GTH_AVCC | -- | |||
EN_0V9_GTY_AVCC | PG_0V9_GTY_AVCC | -- | |||
EN_1V8_VCC_ADC | -- | -- | |||
3 | EN_1V2_PS_DDR | PG_1V2_PS_DDR | 10µs
|
200ms | -- |
| EN_1V2_PL_DDR | PG_1V2_PL_DDR | -- | |||
EN_2V5_PL_DDR | PG_2V5_PL_DDR | -- | |||
EN_2V5_PS_DDR | PG_2V5_PS_DDR | -- | |||
| EN_1V2_GTH_AVTT | PG_1V2_GTH_AVTT | -- | |||
| EN_1V2_GTY_AVTT | PG_1V2_GTY_AVTT | -- | |||
4
| EN_VTT_PS_DDR | -- |
10µs
|
200ms
| -- |
EN_0V85_PS_GTR_AVCC | PG_0V85_PS_GTR_AVCC | -- | |||
EN_VTT_PL_DDR | -- | -- | |||
EN_1V8_GTH_AUX | -- | -- | |||
EN_1V8_GTY_AUX | -- | -- | |||
5 | EN_1V8_PS_GTR_AVTT | PG_1V8_PS_GTR_AVTT | 10µs | 200ms | -- |
6 | PG_SOM | -- | 0µs | 200ms | -- |
1. Defines the delay from when the master enable is asserted before output enable is asserted, or from when Power Good is asserted until the next rail or group's output enable is asserted.
2. Defines the qualification window for which Power Good must be asserted, after output enable is asserted.
JTAG UART
As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.
The command "nios2-terminal.exe" in the NIOS II command shell is used to output the CPLD Firmware and PCB revision. In case of power problems the power enable and power good signals will be displayed additionally.
see also https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/jtag-uart-core.html
I2C interface
The CPLD firmware consists of an I2C slave to Avalon MM master bridge Intel FPGA IP, allowing the CPLD registers to be accessed. The device address in the firmware is 0x55, CPLD registers can be accessed via the i2c interface, e.g. in the Linux console with
- i2cget -y 1 0x55 <Index> (for reading) or
- i2cset -y 1 0x55 <Index> <Value> (for writing)
The following table shows the register map for the CPLD interface :
| Index | Byte | Register Name | Read/Write | Description | Default |
|---|---|---|---|---|---|
| 0x0 | [7:0] | SC_REVISION | R | CPLD Firmware Revision | 0x3 |
| 0x1 | [7:0] | PCB_REVISION | R | PCB Revision | 0x2 |
| 0x6 | [7:0] | pwr_en | R | Status of Power Groups
| 0x7F |
| 0x8 | [7:0] | power_good_in[7:0] | R | Status of Power Good Signals
| 0xFF |
| 0x9 | [7:0] | power_good_in[15:8] | R | Status of Power Good Signals
| 0xFF |
| 0xA | [7:0] | seq_nfault | R | Status of Power Sequencer (Active Low) | 0x1 |
| 0xE | [7:0] | pwr_usb_ena | R/W | Enables/Disables output signal 'SC_EXT_2'
| 0x0 (0x1 in Reference Design) |
Reference Design
In the reference design, the I2C interface in u-boot is used to read out the CPLD and PCB revision as well as to switch on the output signal 'SC_EXT_2' for the USB voltage on the carrier board TEBT0865. These information will be displayed while booting the reference design as shown:
U-boot snippet reference design
Reset
The reset signals ‘MR’ and ‘nRST_SYS’ will be released after power group 6 has been activated.
Appx. A: Change History
Revision Changes
- REV02 to REV03
- changed top design from block design to text design
- added power sequencer
- added debouncing for power good signals
- added jtag_uart
- added i2c interface
- added release for reset (MR and nRST_SYS)
- added logic for SC_EXT_2
- enable/disable USB power for TEBT0865 via I2C
- default: disabled
- update constraining design
- REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | Firmware Release |
|---|---|---|---|---|---|---|
| REV03 | REV02 | Update Change History | SC-PGM-TE0865-02_SC0865-03_20240918.zip | |||
2024-09-18 | v.38 | REV03 | REV02 | Manuela Strücker | Documentation initial release | |
| All |
Appx. B: Legal Notices
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Technology Licenses
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