• Last modified: Oct 14, 2026

Description for the newest Design Version

  • TE0873 Reference_Design
    • Vitis/Vivado 2025.2
    • MicroBlaze V (RISC-V)
    • MDM JTAG UART
    • SDR-SDRAM 64 MByte (AXI4 SDRAM controller, 50 MHz)
    • QSPI Flash (boot from PDI)
    • LED
    • VIO

Basic Documentation and Notes

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