TE0873 Reference Design

Overview

This example contains a simple MicroBlaze V (RISC-V) design for the Spartan UltraScale+ module TE0873. The processor runs an endless loop application, which prints "Hello Trenz Module TE0873" on the MDM JTAG UART and lets the user LED blink. The 64 MByte SDR-SDRAM on the module is accessible over an AXI4 SDRAM controller.

Refer to http://trenz.org/te0873-info for the current online version of this manual and other available documentation.

Key Features

• Vitis/Vivado 2025.2
• MicroBlaze V (RISC-V)
• MDM JTAG UART
• SDR-SDRAM 64 MByte (AXI4 SDRAM controller, 50 MHz)
• QSPI Flash (boot from PDI)
• LED
• VIO

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0873 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   _create_win_setup.cmd/_create_linux_setup.sh

   ------------------------Set design paths----------------------------
   -- Run Design with: _create_win_setup
   -- Use Design Path: <absolute project path>
   --------------------------------------------------------------------
   -------------------------TE Reference Design---------------------------
   --------------------------------------------------------------------
   -- (0)  Module selection guide, project creation...prebuilt export...
   -- (1)  Create minimum setup of CMD-Files and exit Batch
   -- (2)  Create maximum setup of CMD-Files and exit Batch
   -- (3)  (internal only) Dev
   -- (4)  (internal only) Prod
   -- (c)  Go to CMD-File Generation (Manual setup)
   -- (d)  Go to Documentation (Web Documentation)
   -- (g)  Install Board Files from Xilinx Board Store (beta)
   -- (a)  Start design with unsupported Vivado Version (beta)
   -- (x)  Exit Batch (nothing is done!)
   ----
   Select (ex.:'0' for module selection guide):

2. Press 0 and enter to start "Module Selection Guide"
3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note: Select correct one, see also Vivado Board Part Flow

4. Create hardware description file (.xsa file) and export to prebuilt folder

   run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")

   TE::hw_build_design -export_prebuilt

   Using Vivado GUI is the same, except file export to prebuilt folder.

5. Generate Programming Files (*.pdi and *.mcs file for QSPI Flash) with Vitis

   run on Vivado TCL (Script generates applications and bootable files, which are defined in "<project folder>\sw_lib\apps_list.csv")

   TE::sw_run_vitis -all
   TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

   TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

   • latest "hello_te0873.elf" application should reside in "<project folder>\firmware\microblaze_riscv_0\" now
   • Regenerate Vivado Project or update Bitfile only, with new "hello_te0873.elf" associated to the MicroBlaze V processor

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   run on Vivado TCL (Script programs boot image *.pdi on QSPI flash)

   TE::pr_program_flash -swapp hello_te0873

3. Power your board OFF and ON to start the application and see the output on the JTAG UART console

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect JTAG USB

3. Select QSPI as Boot Mode

   Note: See TRM of the Carrier, which is used.

4. Power On PCB

   boot process

   1. Spartan UltraScale+ loads the boot image (*.pdi) from QSPI Flash, the PLM configures the FPGA with the bitstream including the "hello_te0873.elf" application in local BRAM

   2. hello_te0873.elf application starts on MicroBlaze V

   3. "Hello Trenz Module TE0873" will be printed on the JTAG UART console and the user LED blinks

JTAG UART

The design has no physical UART. Console output (stdin/stdout) is routed over the UART of the MicroBlaze Debug Module (MDM) and is available on the JTAG connection.

1. Start XSDB (Vitis installation) and open the JTAG terminal:

   run on XSDB

   connect
   targets -set -filter {name =~ "MicroBlaze*#0"}
   jtagterminal

2. Alternatively use the JTAG UART console of the Vitis debugger.

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
  • probe_out0: Active Low External Reset of the processor system and SDRAM controller (default: 1)
• Monitoring:
  • probe_in0: AXI GPIO bit 0, toggles with the LED of the hello_te0873 application

System Design - Vivado

Block Design

The block design contains a MicroBlaze V (RISC-V) processor with 128 KByte local memory, MicroBlaze Debug Module with JTAG UART, AXI Interrupt Controller, AXI Timer, AXI GPIO for the user LED, VIO for reset control and the Trenz AXI4 SDRAM controller ("<project folder>\ip_lib\sdram_axi_te") for the 64 MByte SDR-SDRAM.

The 100 MHz reference clock is used by a clocking wizard to generate 100 MHz for the processor system and 50 MHz for the SDRAM controller. The AXI SmartConnect bridges between both clock domains.

Address Map

Constraints

Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 63 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]

#
#
#

Design specific constraints

set_property PACKAGE_PIN AC17 [get_ports clk_100MHz]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100MHz]

set_property PACKAGE_PIN AB21 [get_ports B45_LED1]
set_property IOSTANDARD LVCMOS33 [get_ports B45_LED1]

# =====================================================================================================
# IS42S16320F-6BL  SDR-SDRAM  (512Mbit, 32M x16, 4 Banks)
# -----------------------------------------------------------------------------------------------------
#   * 3.3V device, connected banks use VCCO 3.3V.
#   * A13 is not connected on this SDRAM density and therefore not constrained.
#   * Controller and SDRAM run at 50 MHz (CL2), no additional I/O timing constraints are used.
# -----------------------------------------------------------------------------------------------------

# ---- Address ----
set_property PACKAGE_PIN T22  [get_ports {sdram_a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[0]}]
set_property PACKAGE_PIN U23   [get_ports {sdram_a[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[1]}]
set_property PACKAGE_PIN AE24 [get_ports {sdram_a[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[2]}]
set_property PACKAGE_PIN AD24 [get_ports {sdram_a[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[3]}]
set_property PACKAGE_PIN V24  [get_ports {sdram_a[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[4]}]
set_property PACKAGE_PIN U24  [get_ports {sdram_a[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[5]}]
set_property PACKAGE_PIN W25  [get_ports {sdram_a[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[6]}]
set_property PACKAGE_PIN P20  [get_ports {sdram_a[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[7]}]
set_property PACKAGE_PIN P23  [get_ports {sdram_a[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[8]}]
set_property PACKAGE_PIN W23  [get_ports {sdram_a[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[9]}]
set_property PACKAGE_PIN V23   [get_ports {sdram_a[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[10]}]
set_property PACKAGE_PIN N21  [get_ports {sdram_a[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[11]}]
set_property PACKAGE_PIN U25  [get_ports {sdram_a[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_a[12]}]

# ---- Bank address ----
set_property PACKAGE_PIN AD25 [get_ports {sdram_ba[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_ba[0]}]
set_property PACKAGE_PIN T20  [get_ports {sdram_ba[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_ba[1]}]

# ---- Clock / control ----
set_property PACKAGE_PIN V25  [get_ports sdram_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_clk]
set_property PACKAGE_PIN Y25  [get_ports sdram_cke]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_cke]
set_property PACKAGE_PIN R20  [get_ports sdram_csn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_csn]
set_property PACKAGE_PIN R22  [get_ports sdram_rasn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_rasn]
set_property PACKAGE_PIN AC25 [get_ports sdram_casn]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_casn]
set_property PACKAGE_PIN U22  [get_ports sdram_wen]
set_property IOSTANDARD LVCMOS33 [get_ports sdram_wen]

# ---- Data mask ----
set_property PACKAGE_PIN AB23 [get_ports {sdram_dqm[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dqm[0]}]
set_property PACKAGE_PIN T23  [get_ports {sdram_dqm[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dqm[1]}]

# ---- Data ----
set_property PACKAGE_PIN AA24 [get_ports {sdram_dq[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[0]}]
set_property PACKAGE_PIN AE22 [get_ports {sdram_dq[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[1]}]
set_property PACKAGE_PIN AA25 [get_ports {sdram_dq[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[2]}]
set_property PACKAGE_PIN AA23 [get_ports {sdram_dq[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[3]}]
set_property PACKAGE_PIN AB24 [get_ports {sdram_dq[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[4]}]
set_property PACKAGE_PIN AE23 [get_ports {sdram_dq[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[5]}]
set_property PACKAGE_PIN AB25 [get_ports {sdram_dq[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[6]}]
set_property PACKAGE_PIN Y23  [get_ports {sdram_dq[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[7]}]
set_property PACKAGE_PIN R23  [get_ports {sdram_dq[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[8]}]
set_property PACKAGE_PIN R25  [get_ports {sdram_dq[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[9]}]
set_property PACKAGE_PIN P24  [get_ports {sdram_dq[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[10]}]
set_property PACKAGE_PIN P25  [get_ports {sdram_dq[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[11]}]
set_property PACKAGE_PIN N24  [get_ports {sdram_dq[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[12]}]
set_property PACKAGE_PIN N25  [get_ports {sdram_dq[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[13]}]
set_property PACKAGE_PIN N23  [get_ports {sdram_dq[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[14]}]
set_property PACKAGE_PIN N22  [get_ports {sdram_dq[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sdram_dq[15]}]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

hello_te0873

Trenz Hello World example as endless loop. The application prints "Hello Trenz Module TE0873 (Loop: <n>)" on the JTAG UART and toggles the user LED every second over the AXI GPIO IP core.

Template location: "<project folder>\sw_lib\sw_apps\hello_te0873"

Additional Software

No additional software is needed.

App. A: Change History and Legal Notices

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